July 2004
SoC Architecture Simplifies Design of
Integrated Voice and Data Systems For the Network Edge
BY JONATHAN PEACE
The much heralded arrival of VoIP
to the enterprise brought with it the promise of large reductions in
operating expense through the unification of voice and data systems, as well
as the possibility of new applications previously either difficult or
impossible to implement. One of these is the so called �office in a box,� a
union of the traditional PBX with a WAN router, firewall, VPN, and VoIP
gateway.
Exciting new applications,
however, cannot sacrifice any of the performance or features which customers
have come to expect from their legacy systems. In order to meet these
demands, system developers need a cost-effective, flexible platform on which
to build the broad variety of applications and features that users require,
but which at the same time meets the highest quality of service (QoS)
expectations of their customers.
VoIP PROCESSOR EVOLUTION
Early enterprise media gateway designs generally adopted a network processor
+ discrete DSP architecture. This �bolt-on� approach was suitable for low
channel counts. It gradually gave way to integrated DSP and packet
processors due to cost, performance, and scalability requirements. Such
devices are commonly referred to as Media Stream Processors, or MSPs, and
typically perform all processing of the voice path, such as echo
cancellation, voice compression, tone detection, and packet loss
concealment. MSPs are controlled by a separate host controller, which itself
can be relieved of all fast path processing responsibility.
The MSP, often with integrated
Ethernet or other packet interface, solves the problem of performance and
scalability, but provides only part of the functionality required for the
�office in a box.� The other part, the host controller, actually provides a
rich set of functionality including system control, telephony, packet and
router signaling, authentication, key negotiation, storage access and much
more.
For the first time, we are
starting to see the introduction of devices that integrate all of the above
functions, providing a true single-chip solution for �office in a box�
products.
APPLICATIONS CHALLENGES
The applications encompassed by the �office-in-a-box� processor architecture
are extremely broad, covering a wide range of media processing and
networking applications.
The challenge facing mixed-media equipment system designers for this broad
range of applications is to provide an extremely rich variety of
application-level functionality, while at the same time guaranteeing
interactive media performance and system security for large numbers of
simultaneous users.
OFFICE-IN-A-BOX SoC SOLUTION
The �office in a box� system-on-a chip (SoC) architecture described here
solves this problem by logically and physically separating the hard
real-time and soft real-time functions on the die, but provides a clean and
well defined mechanism for communication between the two halves. The core of
the architecture (Figure 1) is comprised of the Media Stream Processor (MSP)
and the Control and Signaling Processor (CSP).
The MSP is responsible for all delay sensitive media processing within the
device, and in this case contains three main elements:
� a high-performance voiceband
signal processor;
� a RISC network processor with hardware acceleration for specific
functions; and
� a hardware cipher engine with Internet key exchange (IKE) acceleration
support.
The CSP is responsible for the
both the control of the MSP and processing of delay insensitive, or bulk,
data. In order to support this requirement it has a large memory space and
MMU, and a full complement of peripherals for system expansion and control.
The two main subsystems communicate over a shared memory interface, which is
abstracted in the CSP as an Ethernet interface by a virtual Ethernet driver.
The separation of the two main functions of the system has many advantages
for the systems designer. The MSP includes pre-tested software that performs
all of the voice and data encapsulation processing with low-latency and
guaranteed performance. This binary, or microcode, performs all voice
processing including echo cancellation, voice coding, and packetization,
from TDM to cell or packet interface. Since the code is pre-tested and runs
with guaranteed resources, it can maintain a high quality level whatever
applications may be running on the CSP.
The CSP can run any common embedded operating system such as VxWorks and
Linux. Applications executing on the CSP are completely independent of the
MSP processing. One significant advantage of running non real-time operating
systems such as Linux or OpenBSD is that it gives designers access to an
enormous wealth of open-source code that can be quickly and easily ported to
the CSP.
SOLVING SYSTEM DESIGN CHALLENGES
The debate over big versus little endian code is not likely to go away any
time soon, and can present a problem any time code written for one endianess
is mixed with code of the opposite flavor. The MSP/CSP approach elegantly
solves this issue. The MSP communicates directly with all fast path
peripherals but exposes all control and data planes over virtual Ethernet
interfaces, limiting the inter-processor interaction to a single device
driver, which can be supplied as source code with the device.
Another challenge facing
designers is the debate over using a Memory Management Unit, or MMU. For
feature-rich environments such as the �office in a box,� access to large
program and data memory space is essential, as is the ability to run
applications not permanently resident in memory, such as Java for example.
For these reasons, an MMU is highly desirable. However, for the highest
performance, especially as it relates to interrupt handling of small packets
typical in a packet voice system, the time associated with switching MMU
context can extract a significant performance penalty. The MSP/CSP
architecture sidesteps this issue, by allowing each processor to do what it
does best, with or without MMU.
The clean abstraction of the
virtual Ethernet interface provides another valuable side-benefit. Existing
application code can be quickly hooked up to the MSP, often achieving �first
voice� in a matter of days, allowing quick and easy evaluation and
prototyping of new systems.
SECURE WATERTIGHT COMPARTMENTS
The MSP/CSP model also provides physical separation of media stream from
applications, greatly reducing vulnerability to attacks that attempt to
manipulate the host processor program counter, such as �buffer overflow
exploits.� This provides the system designer with an extra level of built-in
security, which is especially important as more and more valuable content is
streamed through the device, for example in video-on-demand applications.
UNIFIED MEMORY ARCHITECTURE
To reduce overall system cost, the processor design can employ a unified
memory architecture in which the MSP and CSP share a single external
commodity SDRAM, either SDR or DDR. In addition, a large on-chip SRAM could
provide ample buffer space for the peripheral DMA engines to buffer traffic.
Each of these memory subsystems should be accessed at the same time without
contention.
PROGRAMMING MODEL
The virtual Ethernet driver source code is supplied for a number of
operating systems, and can be easily ported to others. After system boot,
the MSP appears to the CSP as a host on an Ethernet network. Referring to
Figure 2, assume that the CSP wishes to instruct the MSP to perform the
following functions:
� take cells from Utopia and
perform AAL5;
� then look for specific RTP stream from the resulting IP packets;
� then render those packets through a G.723 codec;
� perform G.168 Echo Cancellation; and
� output voice channel to TDM timeslot 38.
In this case, the CSP application
simply sends a set of high-level commands over one of the virtual Ethernet
interfaces, with the above commands encoded using a straightforward API.
The virtual Ethernet model, while
removing the need to write device drivers, has another side benefit:
scalability. MSP processing can be scaled smoothly and with no code changes
by adding extra MSP capacity externally to the device, but connected to the
system master over Ethernet using an off-the-shelf Ethernet switch chip.
The virtual Ethernet abstraction
is used not only for control but also when the CSP wishes to inspect or
modify the fast-path traffic. To facilitate this, the system employs a
zero-copy architecture for any fast path traffic that needs to be handled by
the CSP. For instance, in the example above, after segmentation and
reassembly, any of the IP traffic not destined for TDM would be passed to
the CSP for further processing, e.g., firewalling, routing or network
address translation (NAT). The supplied virtual Ethernet driver performs
this function with no additional copies, reducing both memory bandwidth and
processor overhead.
CONCLUSION
Integrating separate media stream and signal processors on a single chip
offers a new level of silicon integration and cost effectiveness to
designers of access and network edge equipment and applications. The
processor architecture offers a cost effective, high-performance, and
scalable platform on which to build the extremely broad variety of
applications and features, which users demand, along with the carrier class
voice quality and performance that those same users have come to expect.
Jonathan Peace is CTO,
Mindspeed Technologies�
Multiservice Access Division. Mindspeed Technologies designs, develops, and
sells semiconductor networking solutions for communications applications in
enterprise, access, metropolitan, and wide-area networks.
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