December 1998

VLSI: Redesigning The Network Access Landscape

BY DAN UPP

The increasing demand for Internet access is transforming our approach to network access in general. At the same time, the possibilities of silicon technology continue to expand as the common denominator for real estate size shrinks from 0.35 micron to 0.25 micron design rules and below. Highly sophisticated systems on single chips will become the norm at these geometries. So the pressing question becomes: How do we design new network access devices to meet today's needs while anticipating tomorrow's inevitable changes?

NETWORK ACCESS TODAY
Most of the access systems in use today are voice oriented, and current Internet access predominantly means dial-up modems for residential subscribers. However, dial-up technology is mature - next-generation modems beyond 56 Kbps are not possible for a variety of reasons - yet subscribers continue to expect increasingly faster connections to the Internet. Additionally, new access systems are likely to be multi-service.

The common point of access in most cases is the existing copper loop. Higher bandwidth access is possible using several digital subscriber loop (DSL) technologies, and a number of DSL implementations are contending for this market, with some variety of ADSL currently in the lead. With access demand real and immediate, questions of line speed and modulation technology, among other issues, must be resolved. There is also the fundamental debate on whether line transport will consist of direct IP frames or ATM cells. Economics, of course, is the central consideration underlying the access question. How can both service and equipment suppliers make money?

THE SYSTEM IS THE CHIP
Many of these issues can be addressed by system-level semiconductor solutions, which are able to resolve many conflicting requirements successfully. System cost, continually forced downward by competitive pressures, is always a limitation, yet the ability to deal with unforeseen changes and the need for equipment vendors to differentiate their products puts a premium on flexibility.

As device geometry continues to shrink, circuit densities multiply, and time-to-market pressures mount for communication systems designers, a new paradigm has emerged: the silicon defines the system at the hardware level. Today, most design follows a top-down methodology, flowing from system requirements through architecture to implementation, typically in ASICs (application specific integrated circuits). The newest generation of VLSI (very large scale integrator) devices reverses this flow - design begins with the silicon first. By offering a combination of raw power and high versatility, these new devices offer systems manufacturers the ability to map their unique system design specifications into standard silicon components. This approach shortens the time-to-market while keeping a lid on costs. However, for this method to be successful VLSI vendors need to understand the total system requirements.

While ASICs allow manufacturers to meet their system requirements exactly, changes in market demands or standards can stretch design cycles and cause expensive reworking. On the other hand, readily available merchant VSLI devices can reduce risk and enable engineers to meet design times. To date they have been utilized as well-defined subsystems. T1 framers and voice CODECs are the best early examples, with the design space expanding to other functions such as SONET/SDH overhead processing, and tributary mapping more recently.

While providing users with complete off-the-shelf solutions to functional needs, merchant components have minimal effect on system architecture: they are simply "black boxes." The latest very high density system-level devices actually reverse this paradigm by defining the system physical implementation for a class of systems. Designers can quickly implement highly featured, cost effective systems that meet their unique requirements with standard silicon. The functional elements that comprise these new devices include:

• One or more user-programmable RISC (reduced instruction set computer) processors.
• Hardware blocks controlled as RISC co-processors.
• Fixed-function hardware blocks.

Performance is achieved by the smaller-geometry silicon implementation; flexibility by user programming. Users can effect broad control over device functionality by customizing the RISC processor control software. Two keys to ensuring both high performance and versatility are the architecture of the chip itself and the ease of control code development in the internal RISC processors.

Task-Specific Architecture
Programmable VLSI solutions are designed to implement systems with a specific range of applications and class of performance. Next-generation ATM or packet-based devices are especially suited to access systems, the point at which subscribers connect to the network. The requirements of a class of systems are addressed within the architecture by the types of hardware modules selected, by the number and speed of RISC processors incorporated, and particularly by the manner in which these blocks interoperate internally. No solution can be the optimum choice for every system, but elements common to certain types of systems allow one VLSI device to satisfy many needs. By structuring device architecture for a class of applications and incorporating the right elements to meet system requirements, a balance of performance, versatility, and cost effectiveness can be achieved.

The required hardware blocks are determined by the intended class of systems for the device. Fixed-function blocks for external interfaces such as UTOPIA, memory, buses, and boundary scan are well-defined. While there may be some discussion of mode selection, block design is straightforward. Other hardware blocks are designed for specific subsystems, and this is the main area of internal hardware-software tradeoffs.

Performance Versus Versatility
Which functions should be designed in gates to ensure performance and which should be coded in software for versatility? One example is illustrated by the function of address translation and table lookup for ATM cells. Although this could be executed in software, the number of RISC processor instruction cycles is relatively large and can limit device throughput. A programmable hardware block is implemented instead, resulting in significant performance improvement. To retain user flexibility in table and translation structures, the function can be incorporated as a software-controlled co-processor attached to a RISC processor. This methodology is followed throughout the device design. Fixed-function and co-processor hardware blocks are chosen to ensure a high level of performance for access applications. The chief advantage of having several hard-wired functions is efficient handling of all critical real-time device functions. One or more RISC processors are used in addition to the hardware blocks, both to control co-processors and to execute higher level non-real-time functions.

Predictable Coding
The use of embedded RISC processors requires architectural discipline to ensure that the end product will indeed be user-programmable. Internally and externally, processors should communicate only through messages. No hardware interconnections are permitted which do not fit into the devices internal architecture. While such "sneak paths" can provide performance improvements, their effect on software can be unpredictable, making code generation or modification nearly impossible. Also, software in internal processors cannot be debugged using standard test equipment. Specific hardware is included in all devices to provide those functions normally used in debugging via a scan interface port - single-step, breakpoints, and trace, among others. All RISC software is downloaded over the scan interface or an alternative connection.

The complete device architecture consists of hardware blocks and RISC processors within an internal architecture optimized for performance over a specific range of applications. The result is an off-the-shelf VLSI product that is suited to building particular access systems and remains flexible to meet a manufacturer's system requirements. By concentrating on design for application-specific architecture, a much higher level of performance and serviceability is achieved than could be attained by a simple combination of RISC processors and programmable logic.

A PROGRAMMABLE SOLUTION FOR ACCESS SYSTEMS
A further topic for discussion is software architecture and development tools that facilitate user programmability for these application-specific VLSIs. An example of a programmable architecture for access applications is a network-layer processor. It is fully customer-programmable and capable of supporting both cell and frame-based applications with firmware definition. When a number of these components are interconnected over a 32-bit parallel bus, they form a powerful, versatile access multiplexer platform. In addition to task-specific circuitry for maintaining high throughput, the device might contain embedded RISC microprocessors and utilize external SSRAM to support queuing - both ingress and egress - as well as table storage for performance monitoring and translation, creating cost effective storage space. Each of the RISC processors would be programmable by the user, delivering both power and flexibility to support the demands of different system vendors.

The network-layer processor could support a dual bus interface to provide access at a rate of around 2 Gbps. For example, an xDSL access system would consist of commercial line modems, several processors, and SSRAM and system microprocessors. With device firmware and system software, such a system could be provisioned for any type of xDSL and operated in either cell or frame mode. Moreover, major system upgrades could be executed by downloading new firmware into the network processors even after initial deployment. Changes could be introduced which previously would have called for ASIC device modifications or expensive field retrofits. Equipment products could be brought to market faster with the knowledge that required upgrades would be easily handled.

EFFECTIVE ACCESS NETWORK DESIGN
The following points summarize the main criteria to bear in mind in developing VLSI solutions for access applications:

• Communications IC architecture must be designed to match a specific range of tasks.
• Designers can take advantage of advances in semiconductor technology to meet a variety of requirements. Small geometries deliver a higher level of functionality and increased speed, producing denser, faster, cheaper products. Aggressive use of multiple RISC processors will help ensure programmability.
• There is an ever-increasing demand for memory: More is never enough. Memory can be configured either inside or outside the chip, based on speed and density requirements.
• The most important consideration is making the design user-friendly by developing built-in testing tools and task-specific device architecture. Network ICs will define the architecture rather than simply implement it.

Advances in VLSI technology development are increasingly evident in the semiconductor process improvements that continue to drive down cost and power per function, increase speed per function, and reduce the number of devices through functional integration. System level requirements for the access market are dynamic and are reaching new levels of complexity. Concurrently, advancements in IC technology have raised the degree of chip functionality to that of system level devices.

Leading semiconductor suppliers will continue to apply the principles of programmable RISC "engines" and task-specific architecture to develop VLSI devices with the widest possible applicability. With the continued evolution of semiconductor technology, these same concepts will produce future generations of faster devices with ever-higher functional density. Powerful VLSI solutions based on these principles will continue to catalyze the growth of the access market.

Dan Upp is vice president of technology development at TranSwitch Corp, and he is also a member of IEEE and the ATM Forum. Headquartered in Shelton, Connecticut, TranSwitch Corporation specializes in the design, development, and marketing of highly integrated digital and mixed-signal semiconductor solutions for the telecommunications and data communications markets. For more information, please visit TranSwitch's Web site at www.transwitch.com.