September 2001

 
Packet-Switching Standard Supercharges High Availability

BY ED BIZARI 

With vendors already offering off-the-shelf products compliant with the new 2.16 specification, architects of H/A systems can explore the potentials by answering this question: "Do I continue designing increasingly complex, tightly coupled systems to meet project requirements, or should I consider the PICMG 2.16 approach to building more capable systems on a distributed model?" The decision becomes simple when one understands the benefits of PICMG 2.16: Greater bandwidth, simplified integration, inherent high-availability features, and easily extensible and reduced time-to-market capabilities.

The concept is to move system traffic from CompactPCI's shared-bus architecture to a packet-based, fault-tolerant, embedded, switched 10/100/1000 Mbit/sec Ethernet network. Bringing high-speed Ethernet into the CompactPCI backplane leverages the ubiquity and commodity status of these existing high-volume components and technologies. Systems designers can readily use these evolutionary technologies to develop revolutionary solutions, such as the concept of an embedded system area networks (ESANs), and redundant, fault-tolerant Ethernet networks within a CompactPCI chassis.

Rollout of systems based on the PICMG 2.16 specification will occur quickly. Developers will have the ability to build high-density, high-availability systems without having to wait for complex architectures or new silicon to be developed. As was the case with the CompactPCI itself, this new spec adapts existing technology for industrial purposes. Because 2.16 extends rather than replaces CompactPCI, neither financial nor time investment in earlier development is wasted.

The Basics
There are two underlying concepts: (1) CompactPCI embeds an Ethernet infrastructure in the midplane, accessible via the P3 connector and with all "node slots" in the chassis interconnect through purpose-built switching "fabric slots;" and (2) node cards operate as stand-alone "systems in a slot," interfacing with each other through a network stack such as TCP/IP. Together, system performance and reliability are increased, and component costs and design complexity are reduced.

Ethernet within the chassis provides a radically new way to develop H/A and next-generation IP-telephony systems. System level functionality (cards) can act as power subsystems with their own processor, OS, and memory, and can communicate independently with other cards via Ethernet. Because the platform accommodates two fully redundant networks within a single chassis, potential systems' losses are limited to a single slot in a chassis, which is the ultimate hot-swap fail-safe. Meantime, the driver/backplane level no longer requires integration, as it ascends to the network and transport layers because nodes in the chassis become operating-system agnostic or driverless. Overall, this means simpler design models and significant time savings.

It's also faster. The PICMG 2.16 specification offers throughput rates up to 40 Gbit/sec full duplex, more than an order-of-magnitude improvement over CompactPCI implementations. Bused architectures allow single conversations operating at 66 MHz over a 64-bit data bus to provide a ~4 Gbit/sec transfer rate between only five slots. The new specification allows two switching fabrics, each supporting 20 simultaneous conversations at 2,000 Mbit/sec (for a 40-Gbit/sec transfer rate).

2.16 supports up to 19 node slots using a single fabric (packet-switching) slot in a 19-inch CompactPCI chassis, with hot-swappable node slots communicating via the redundant switching, hot-swappable fabric slots. Using just eight active pins on P3 per link port, packet-switching backplane performance can range from 4,000 Mbit/sec (with a single 100 Mbit/sec fabric) to 40 Gbit/sec (with dual-switched Gbit fabrics) full duplex. "Virtual backplanes" can be created expanding to any number of CompactPCI (or non-CompactPCI) systems by running either fiber or CAT5 Ethernet cables to external connections that extend the packet-switched bus.

The Potential
PICMG 2.16 preserves the H.110 capabilities and the mechanical, power, and hot-swap attributes of CompactPCI while significantly improving performance, scalability, and reliability. System components can be mixed with units relying on the CompactPCI bus and interact within the same chassis. Building sub-systems around preserved legacy CompactPCI elements means system capabilities can be created organically and gradually onto the new framework, with systems evolving to fit needs without rendering earlier design work obsolete.

Meantime, hard wiring connections between sub-systems using the new spec offers advantages over traditional Ethernet practices. Mean time between failure (MTBF) and reliability are improved. For example, cables and connectors -- the LAN elements most prone to failure -- are eliminated, creating a more reliable network. It also minimizes set-up mistakes and cable-plant configuration issues.

All designers strive to build systems that are less expensive, smaller, and more dependable. First-generation architectures were quick to market, but not sufficiently reliable for telecom-related applications. Second-generation architectures that took advantage of CompactPCI standards were an improvement, but remain limited to their shared-bus nature. With this generation, it's time to get off the bus.

Ed Bizari is director of marketing at Performance Technologies, Inc. Performance Technologies is a leading supplier of packet-based telecommunications and networking products that enable convergence of wireline, wireless, and next-generation Internet Protocol networks.

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