AMD and IBM Advocate Using Immersion and Ultra Low-K in 45nm Chips

By Niladri Sekhar Nath

TMCnet Contributing Editor

 

IBM (News - Alert) and AMD have jointly emphasized on the use of immersion lithography, ultra-low-K interconnect dielectrics, and multiple enhanced transistor strain techniques for application to the 45nm microprocessor process generation at the International Electron Device Meeting (IEDM). Both the companies are planning to introduce the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics in mid-2008.

 

“Immersion lithography will allow us to deliver enhanced microprocessor design definition and manufacturing consistency, further increasing our ability to deliver industry-leading, highly sophisticated products to our customers,” said Nick Kepler, vice president of logic technology development at AMD. “Ultra-low-K interconnect dielectrics will further extend our industry-leading microprocessor performance-per-watt ratio for the benefit of all of our customers.”

 

Current process technology uses conventional lithography, that can’t define microprocessor designs beyond the 65nm process technology generation. On the other hand, immersion lithography uses a transparent liquid to fill the space between the projection lens of the step-and-repeat lithography system and the wafer that contains hundreds of microprocessors.

 

Lithography provides increased depth of focus and enhanced image fidelity that can improve chip-level performance and manufacturing efficiency. This immersion technique will help AMD and IBM develop a production-class immersion lithography process for the introduction of 45nm microprocessors.

 

According to the news release, the ultra-low-K dielectrics reduces interconnect capacitance and wiring delay to enhance microprocessor performance as well as lower power dissipation. The advancement helps development of an industry-leading ultra-low-K process integration that reduces the dielectric constant of the interconnect dielectric while maintaining the mechanical strength.

 

“The introduction of immersion lithography and ultra-low-K interconnect dielectrics at 45nm is an early example of the successful transfer of technology from our ground-breaking research work at the Albany Nanotech Center to IBM’s state-of-the-art 300mm manufacturing and development line at East Fishkill, New York, as well as AMD’s state-of-the-art 300mm manufacturing line in Dresden, Germany,” said Gary Patton, vice president, technology development at IBM’s Semiconductor Research and Development Center. “The successful integration of leadership technologies with AMD and our partners demonstrates the strength of our collaborative innovation model.”

 

IBM and AMD have been working together on the development of next-generation semiconductor manufacturing technologies since January 2003. Both the companies have extended their collaboration until 2011 covering 32nm and 22nm process technology generations in November 2005.