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Magnetic Shielding for Stacked MRAM Packages(Semiconductor International Via Thomson Dialog NewsEdge) Magnetoresistive random access memory (MRAM) is a paradigm-shifting technology that uses magnetic spin properties of electrons instead of their electrical charge to store and transact information. MRAM has been identified as an excellent candidate for a universal memory because it combines the speed of static random access memory (SRAM) and the non-volatility of flash memory.1-5 It also has good reliability characteristics.4,6-10 The Table compares MRAM to other memory technologies. MRAM has not yet found widespread usage in commercial products, but a recent survey identified several military/aerospace applications where there is high demand for solid-state data storage using non-volatile memory technology such as MRAM. MRAM is particularly attractive for solid-state recorders on spacecrafts, where power consumption and radiation tolerance are crucial.4 Another key factor for spacecraft applications is long-term data retention, since space missions often last >10 years.10 Although development activity has centered on military/aerospace applications, there is significant growing interest in MRAMs for commercial products. Potential industrial applications include assembly and robotics, automatic test equipment, visual inspection, optical character recognition, process control, machine vision, supervision, energy production and electronics manufacturing. One roadblock to the commercialization of MRAM is its low density compared with DRAM and NAND flash. For the same technology node, the MRAM cell size is larger than the NAND and DRAM cell sizes (Table11 ), and the minimum feature size is a couple of generations behind DRAM and flash. At press time, the highest-density MRAM die commercially available was the 4 Mb Freescale die in a thin small outline package (TSOP), ~18 10 1.2 mm.12 The second issue is that MRAM operation can be disrupted by external magnetic fields generated by a nearby disk drive or power supply, making it important to magnetically shield the die from such fields. High-density package-on-package technologyEffective density can be substantially improved using stacked chip-scale packages (CSPs) in a package-on-package (PoP) configuration. For example, our stackable CSP (10.8 8.8 0.43 mm), compared with the commercially available TSOP for the same die, has a 57% smaller footprint and is 64% thinner. When stacked eight high (Fig. 1), the memory density per unit board area is 18.6 that of the TSOP. Even higher effective density can be achieved by stacking additional layers. Figure 1 also shows a prototype of a 64-layer package stack. Magnetic shielding The switching field for MRAM is normally in the range of 40-60 Oersted (Oe). Reasonable performance using a simple model of yield allows a total junction-to-junction variability expressed in terms of field variation of ~2-3 Oe. This estimate includes not only external field fluctuations, but also device-to-device tunnel junction switching field variation, overlay errors, neighbor interactions, and other factors. This error budget is critical, since process technology and cell designs are near the limit for 100% yielding chips, even without considering external field fluctuations. Fields perpendicular to the plane can be much larger without significant impact on the device operation. In practice, the specification for electromagnetic noise field varies by chip design. A field of 1 Oe seems to be an acceptable level for the MRAM devices that we have studied. Magnetic fields in a typical operating environment for MRAM can easily exceed 1 Oe. For example, typical fields in most locations inside a computer (excluding obvious trouble sources such as motors) are in the range of a few Oe (static). So, under actual operating conditions, the MRAM shielding specification is recommended as a DC shielding factor (SF) of 25. Such shielding can effectively attenuate a 25 Oe external field to 1 Oe. Magnetic shielding can be achieved by surrounding the region affected by electromagnetic waves with a high-permeability material. The magnetic field is shunted through the material. It is important that the shielding material does not retain significant magnetic charge, lest it become a source of a magnetic field. Provided the shield material does not approach saturation, the two major factors in the shield's effectiveness are the shield material's permeability and geometry. An extensive material search was carried out to identify the best candidates. Five materials were selected as possible candidates and simulated: Moly-permalloy,13 Supermalloy,14 Alloy 42,14 Metglas 2705M,15 and Mushield.16 Based on the material's permeability, availability and price, Metglas 2705M was rated as the best material for multilayer shielding. Multilayer shielding is achieved by attaching a foil shield on the top and/or bottom of the individual CSP prior to stacking. Metaglas 2705M is available in 16 m thickness, and thus is the material most suitable for this shielding geometry. Modeling was carried out using the Quickfield 2-D Magnetic Modeling Program. The model assumes that magnetic flux densities >1 Gauss are detrimental to the operational reliability (error rate) of the MRAM chips. Permeability of the die is assumed to be 1. The model considers both the lead current effect and external magnetic fields. Attenuation of external field through shieldingAn eight-layer stacked PoP was modeled for the multilayer shielding geometry. Layers 1-7 in the stack received a single 16 m thick Metglas foil shield on top of the mold cap. The bottom layer (layer 8) received an additional shield. This geometry proved to be very effective. The shield attenuates a 50 Oe external field to <1 Oe throughout most of the stack (Fig. 2), with the exception of the top and bottom layers, where the shield saturated and allowed the field to exceed 1 Oe. The SF in a 20 Oe horizontal applied field is ~250, which far exceeds the required SF of 25 needed for most environments in a computer. Additional shielding layers can be added if necessary. Modeling for multilayer shielding was carried out using only the Metglas material, because the other four materials selected as possible candidates are not currently available as foils <25 m thick. We also modeled a can-like structure, which is placed over the entire stack. Openings on the bottom of the can are needed to accommodate the electrical solder joints on the package. Four types of materials are modeled: Moly-permalloy, Supermalloy, Alloy 42 and Mushield. For a given thickness, Mushield gives the best results among the four materials. Mushield is available in thicknesses of 2 mil (50.8 m) or 4 mil (101.6 m). Figure 3 shows simulation results for a can made of 50 m thick Mushield in a 20 Oe external field. Because of leakage through the opening for solder joints, the field inside the can is less uniform than the field inside a stack with multiple layers of shielding. A 50 m thick can is not sufficient to attenuate a 20 Oe external field to <1 Oe. Increasing the shield thickness to 100 m should reduce the field in the active memory area to <1 Oe. Field induced by electrical currents in the packageIn addition to an external field that may affect the operation of the MRAM, current flowing through the leads in the package can also generate a magnetic field that could potentially impact the MRAM function. The impact was quantified by modeling. Three current levels (10, 100 and 500 mA) were modeled without a shield in place. A current of 500 mA is substantially higher than the maximum pulse current specified for MRAM devices, and thus represents the worst-case operating condition. In the absence of an external field, the lead currents result in no significant fields in the single-layer MRAM CSP. The fields induced by even a single 500 mA current pulse are <1 Oe and decay rapidly with distance (Fig. 4). Since the edge of the active area of the die is at least 1 mm away from the package lead, the impact from the 500 mA current pulse is negligible. The operating current for the MRAM is significantly lower than the 500 mA used in the simulation. Because only one die in the stack is activated at any given time, the results for the single layer also apply to the stacked package. Experimental verification of modeling resultsMagnetometer sensor die (NVE AA-002-02) were used to verify the modeling results and evaluate the performance of the multilayer shielding solution. The sensors were purchased in wafer form, diced into blocks of multiple sensors, and packaged with the MRAM CSP substrate. Using multiple sensor locations in the package allows for mapping of the magnetic field in different locations of the die and provides information on shielding effectiveness as a function of distance from the edge of the die. To test shielding capabilities, the stacked package was introduced into a uniform magnetic field created by a custom wound solenoid of 51 mm inner diameter and 100 mm length wound, with ~400 turns of 22 AWG magnetic wire. An Agilent E3646 dual-output power supply was used to provide current to the solenoid and a constant voltage of 9 V to the magnetic sensor input. A Sypris Model 6010 Gaussmeter with a standard 1X axial probe was used to calibrate the field vs. current relation inside the solenoid. A pre-packaged NVE AA-002-02 GMR sensor was used to calibrate the sensor output voltage to the field strength. This is the same sensor used inside the magnetic emulator package. The Gaussmeter probe and GMR sensor are both held in the middle of the solenoid by a fixture. An Agilent 34401A digital multimeter was used to measure the GMR sensor output. Figure 5 shows magnetic fields measured by three sensors located at the same X-Y position but different Z positions inside the PoP. The sensor location in the X-Y plane corresponds to the edge of active memory area inside the MRAM die. When the external field is <25 Oe, the shielding limits the magnetic field at all three sensors to <1 Oe. As the external field increases further, the shields at the top and bottom of the stack begin to saturate. At the center of the stack, the shield is effective up to a 50 Oe external field. Correlation between the simulation results and experimatal data is excellent. SummaryMRAM is a promising candidate for universal memory because of its combination of non-volatility, high-speed and conventional CMOS compatibility, as well as its potential for radiation hardness. However, there are some significant issues, such as low density and the potential for disruption by external magnetic fields. PoP stacking technology is one approach designers are using to both improve the packaged storage density and effectively address magnetic shielding. For example, an eight-layer stacked PoP improves storage density 18 over a commercially available TSOP package. A multilayer magnetic shielding solution proved effective in magnetic fields of up to 25 Oe using a commercially available material that can be readily adopted for volume production. Features of MRAM and Other Memory Technologies at the 90 nm Node MRAM NOR flash NAND flash SRAM DRAM Non-volatility Yes Yes Yes No No Endurance (cycles) >1015 >1015 >1015 read, <106 write >1015 >1015 Memory cell size (F2) 20-25 10-15 4-6 50-100 5-10 Performance (MHz) 75-125 (Random read) <133(Random read) <40 (Sequential read) 50-2000 50-350(Random read) Additional cost over CMOS 15-25% 25% 25% 0 15% AcknowledgementThe authors would like to acknowledge the Air Force Research Laboratory for financial support under the Advance MRAM Project and for their permission to publish the results. Guilian Gao joined Tessera as a staff engineer in January 2005. Prior to that, Gao worked as a senior packaging engineer at Zeevo Inc. and as a visiting associate professor at Stanford University. Before her Stanford assignment, Gao was a senior technical specialist at Ford Motor Co. She has a bachelor's degree in materials science and engineering from Beijing University of Aeronautics and Astronautics, a master's degree in material science from the University of Manchester, UK, and a Ph.D. in material science from University of Cambridge, UK. Kenneth Honer is the senior manager of package R&D at Tessera. He has six years of program and product management experience. Prior to joining Tessera in 2004, he was in charge of developing MEMS-based optical components for commercial and military applications at Lightconnect. Honer received a Ph.D. in mechanical engineering with an electrical engineering minor from Stanford University, a master's degree in mechanical engineering from Stanford, and a bachelor's degree in mechanical engineering from U.C. Berkeley. References S.A. Wolf et al., Spintronics: A Spin-Base Electronics Vision for the Future, Science , Nov. 16, 2001. S. Tehrani et al., Magnetoresistive Random Access Memory Using Magnetic Tunnel Junctions, Proc. of the IEEE , May 2003, Vol. 91, No. 5. S. Kaka, Past, Present, and Future of MRAM, Tape Head Interface Committee Meeting, July 2003. L. Adams et al., Challenges in Implementing Commercial Non-Volatile Memory in Spacecraft Solid State Recorders, Proc. Non-Volatile Memory Tech. Symp. , November 2000. B. Kaufman and K. Kiamanesh, A Non-Volatile Solid State Recorder for 100,000 g Environments, Sensors , June 2002. L. Cohn, Non-Volatile Memory Technology Programs at the Defense Threat Reduction Agency, Radiation Hardened Microelectronics Project, Proc. Non-Volatile Memory Tech. Symp. , November 2003, p. 2-1. W.J. Gallagher and S.S.P. Parkin, High-Speed 128Kbit MRAM Core in a 0.18 m CMOS Technology Utilizing PtMn-based Magnetic Tunnel Junctions, Proc. Non-Volatile Memory Tech. Symp. , November 2003, p. 10-1. R. Desikan et al., On-chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories, The University of Texas at Austin, Tech Report TR-02-47, Sept. 27, 2002. A.K. Sharma et al., Evaluation of Data Retention and Imprint Characteristics of FRAMs Under Environmental Stresses for NASA Applications, Extreme Environment Electronics , August 2002, Vol. 8, No. 2. S. Kayali, Reliability Challenges for the Utilization of Non-Volatile Memories in Space Systems, Proc. Non-Volatile Memory Tech. Symp. , November 2000. R. Gordon. Market Focus: MRAM as a Universal Semiconductor Memory Technology, Gartner Inc., 2005. Freescale Semiconductors Data Sheet for MR2A16A. Available at:http://www.freescale.com/files/microcontrollers/doc/data_sheet/MR2A16A.pdf B.D. Cullity, Introduction to Magnetic Materials, Addison Wesley, N.Y., 1972, p. 531. Special Purpose Nickel Alloys, Figure 3, p. 4. Available at: http://www.asminternational.org/Template.cfm?Section=SneakPreview&template=E commerce/FileDisplay.cfm&file=ACF7F5.pdf Technical Bulletin for 2705m alloy. Available at: http://www.metglas.com/downloads/2705m.pdf Design Guide, p. 9. Available at: http://www.mushield.com/documentation/catalog_and_design_guide.pdf Copyright 2006 Reed Business Information. All Rights Reserved. |