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Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe
[June 05, 2023]

Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe

Barcelona, Spain , June 05, 2023 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089ISIN: US03420C1099), a leading provider of high efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier member of RISC-V International, is pleased to announce its diamond sponsor participation in the prestigious RISC-V Summit Europe. This premier event, taking place from June 5 to 8, 2023 in Barcelona, Spain, will feature Andes as a key contributor, presenting a keynote speech, poster publication, and participation in an automotive panel discussion. Additionally, Andes will be showcasing its cutting-edge RISC-V CPU IP solutions at booth #14.

Join Dr. Charlie Su, President and CTO of Andes, as he delivers an engaging keynote titled "RISC-V is Firing on All Cylinders" on June 6 at 12:00 PM. Dr. Su will highlight the rapid adoption of RISC-V across a wide range of applications, from small microcontrollers to AI/ML accelerator systems in data centers. The keynote will provide examples of RISC-V applications and the corresponding solutions to support them and will also explore different approaches for matrix multiplication extension, enabling direct AI/ML acceleration with the RISC-V architecture. Furthermore, Dr. Charlie Su will contribute to a panel discussion on "Automotive/Embedded" on June 6 at 17:30 PM. Andes recently announced its new product line, AndesAIRE™, which offers highly efficient AI/ML solutions for edge and end-point inference. On, June 7, Warren Chen, Andes senior Technical Manager, Marketing, will give a demo presentation titled "Andes AI Runs Everywhere (AndesAIRE™) with DSP/Vector/NN Libraries and AndesClarity" in the demo theater on June 7 at 11:10 AM.

In addition, Andes will proudly showcase development boards with AndesCore-Embedded™ technology at booth #14. These boards include the Tinker V, the first RISC-V Single-Board Computer (SBC) from ASUS IoT; an MPU development board from Renesas; an AI development kit with a camera module from Cnaan; the IT9836 TDDI demo board from ITE; and the PC802SCB 5G small cell reference design from Picocom.

You can learn more about the RISC-V Software Ecosystem (RISE) project on Andes booth #14. “Andes is proud to be part of the newly launched RISE Project, a new open source initiative to accelerate the development of software for RISC-V across a variety of market segments. Hosted by Linux Foundation Europe, RISE will support the global standards activities and achievements of RISC-V International,” said Dr. Charlie Su, CTO and President of Andes Technology and a Director of the RISE Governing Board. Please visit the RISE website for how to join and other information.

This event presents a valuable opportunity for RISC-V enthusiasts to engage in one-on-one discussions with Andes experts, enabling deeper exploration of RISC-V solutions. We invite you to visit booth #14 at the RISC-V Summit Europe and experience live demonstrations of our leading-edge CPU IP technology.

Details of Andes’ sessions during the RISC-V Summit Europe are as follows:
Tuesday, June 6,
•       12:00 - 12:15 PM: Keynote “RISC-V is Firing on All Cylinders” by Dr. Charlie Su, President and CTO
•       17:30 - 18:30 PM: Automotive/Embedded Panel by Dr. Charlie Su, President and CTO
Wednesday, June 7,
•     11:10 - 11:30 AM: Demo Talk “Andes AI Runs Everywhere with DSP/ Vector/ NN Libraries and AndesClarity” by Warren Chen, Senior Technical Manager, Marketing

For more information, please visit the RISC-V Summit Europe website.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533SIN: US03420C2089ISIN: US03420C1099), a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit Follow Andes on LinkedIn?Facebook?Weibo?Twitter?Bilibili and YouTube

Hsiao-Ling Lin
Marcom Manager,
Andes Technology Corp.
[email protected]

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