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Sonics Upgrades Designer Productivity And Power Analysis Capabilities In Next-Generation SoC Development EnvironmentMILPITAS, Calif., June 8, 2015 /PRNewswire/ -- Sonics, Inc., the world's foremost supplier of on-chip network (NoC) technologies and services, today introduced SonicsStudio 8.0, the latest release of its next-generation system-on-chip (SoC) development environment that includes improvements for both designer productivity and power analysis. In Release 8.0, Sonics has added major new features to all three areas of SonicsStudio: the Director user interface, the underlying SonicsStudio generation tools, and the automated development flows for stimulus generation, simulation, synthesis, and performance/power analysis. "No other SoC development environment comes close to SonicsStudio for ease-of-use in graphical design capture with NoCs, accuracy in dynamic power analysis, and seamless, front-to-back design flow integration," said Drew Wingard, CTO of Sonics. "Release 8.0 of SonicsStudio incorporates many new capabilities our NoC customers requested to improve productivity using the environment and produce better quality of results in silicon." SonicsStudio Director User Interface The focus of Release 8.0 is providing additional information in Director's graphical views that enable designers to see at a glance key characteristics of their network, for example:
These improvements to the Director user interface make it much easier to inspect and capture the design. They eable designers to graphically view the clock and power domains and the partitioning. Designers can easily see the width of all the individual links between the NoC routers and agents to quickly perform a visual audit. The re-timing view displays all of the re-timing stages in the different components of the system. If designers are interested in the latency between two components, they can quickly view the entire path and count the number of re-timing stages very directly and intuitively. SonicsStudio Generation Tools Release 8.0 incorporates substantial improvements for designers implementing power-optimized SoCs. For example:
Automated Development Flow Release 8.0 provides more design flow automation for performance and power analysis. On the performance analysis side, a new parser imports the results from RTL or third-party ESL simulators into the Director database format with support for complete, multi-hop transaction tracing. This improves analysis and debug performance for designers whether they are using SystemC, RTL or other simulation approaches. On the power side, the development flow now supports automatic gate-level simulation of collections of Sonics IP using the same traffic patterns from performance simulations together with the extraction of dynamic power results based on the switching activity from these simulations. This makes accurate, push-button dynamic power analysis available much earlier in the design process - early enough to use while considering power partitioning decisions. It is particularly important to use realistic traces when estimating the power of on-chip networks because their distributed nature and asymmetric communication patterns make uniform activity factor-based analysis almost meaningless. The development flow also includes template generation to use the UPF or CPF power intent outputs from socmap in later stages of the customer design flow. This eases integration of SonicsStudio with industry-standard tooling and improves customer usability. Availability SonicsStudio 8.0 is available to early access customers now with general availability in July. For more information on SonicsStudio 8.0, contact your Sonics sales representative. About Sonics, Inc. Contact: Erica Harbison Photo - http://photos.prnewswire.com/prnh/20150605/221242
To view the original version on PR Newswire, visit:http://www.prnewswire.com/news-releases/sonics-upgrades-designer-productivity-and-power-analysis-capabilities-in-next-generation-soc-development-environment-300095109.html SOURCE Sonics, Inc. |