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U.S. Patents Awarded to Inventors in Oregon (Sept. 17)
[September 17, 2014]

U.S. Patents Awarded to Inventors in Oregon (Sept. 17)


(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Sept. 17 -- The following federal patents were awarded to inventors in Oregon.

*** Citrix Systems Assigned Patent ALEXANDRIA, Va., Sept. 16 -- Citrix Systems, Fort Lauderdale, Florida, has been assigned a patent (8,832,300) developed by Robert D. Plamondon, Blodgett, Oregon, for systems and methods "for identifying long matches of data in a compression history." The patent application was filed on Aug. 6, 2012 (13/567,452). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8832300.PN.&OS=PN/8832300&RS=PN/8832300 Written by Marlyn Vitin.



*** Intel Assigned Patent for Load Balancing for Multi-threaded Applications Via Asymmetric Power Throttling ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,839,258) developed by nine co-inventors for "load balancing for multi-threaded applications via asymmetric power throttling." The co-inventors are Ryan Rakvic, Annapolis, Maryland, Richard A. Hankins, San Jose, California, Ed Grochowski, San Jose, California, Hong Wang, Fremont, California, Murali Annavaram, Austin, Texas, David K. Poulsen, Champaign, Illinois, Sanjiv Shah, Champaign, Illinois, John Shen, San Jose, California, and Gautham Chinya, Hillsboro, Oregon.

The patent application was filed on Jan. 20, 2012 (13/354,623). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=88,39,258.PN.&OS=PN/88,39,258&RS=PN/88,39,258 Written by Deviprasad Jena; edited by Jaya Anand.


*** Novellus Systems Assigned Patent ALEXANDRIA, Va., Sept. 17 -- Novellus Systems, Fremont, California, has been assigned a patent (8,795,482) developed by six co-inventors for "[s]elective electrochemical accelerator removal." The co-inventors are Richard S. Hill, Atherton, California, John S. Drewery, Santa Clara, California, Steven T. Mayer, Lake Oswego, Oregon, Timothy M. Archer, Lake Oswego, Oregon, Avishai Kepten, Lake Oswego, Oregon, and Marshall R. Stowell, Wilsonville, Oregon.

The patent application was filed on Aug. 10, 2012 (13/572,483). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8795482.PN.&OS=PN/8795482&RS=PN/8795482 Written by Lesley Gonzales; edited by Vessie Ann Abalos.

*** Intel Assigned Patent for Apparatus and Method for Dynamically Extensible Virtual Switch ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,838,743) developed by Saul Lewites, Aloha, Oregon, and Ajay Garg, Portland, Oregon, for an "apparatus and method for a dynamically extensible virtual switch." The patent application was filed on Feb. 13, 2004 (10/779,083). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,838,743.PN.&OS=PN/8,838,743&RS=PN/8,838,743 Written by Deviprasad Jena; edited by Jaya Anand.

*** Intel Assigned Patent for Sink Device Addressing Mechanism ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,838,758) developed by Srikanth Kambhatla, Portland, Oregon, for a "sink device addressing mechanism." The patent application was filed on Dec. 18, 2012 (13/717,887). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,838,758.PN.&OS=PN/8,838,758&RS=PN/8,838,758 Written by Deviprasad Jena; edited by Jaya Anand.

*** Intel Assigned Patent for Methods and Apparatuses for Processing Wake Events of Communication Networks ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,839,356) developed by five co-inventors for "methods and apparatuses for processing wake events of communication networks." The co-inventors are Michael A. Rothman, Puyallup, Washington, Arvind Kumar, Beaverton, Oregon, Vincent J. Zimmer, Federal Way, Washington, Patrick G. Kutch, Beaverton, Oregon, and Omer Levy, Modiin, Israel.

The patent application was filed on Dec. 31, 2007 (12/006,150). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=88,39,356.PN.&OS=PN/88,39,356&RS=PN/88,39,356 Written by Balkishan Dalai; edited by Jaya Anand.

*** Novellus Systems Assigned Patent for Control of Electrolyte Hydrodynamics ALEXANDRIA, Va., Sept. 17 -- Novellus Systems, Fremont, California, has been assigned a patent (8,795,480) developed by two co-inventors for apparatus and methods "for electroplating one or more metals onto a substrate." The co-inventors are Steven T. Mayer, Lake Oswego, Oregon, and David W. Porter, Sherwood, Oregon.

The patent application was filed on June 29, 2011 (13/172,642). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8795480.PN.&OS=PN/8795480&RS=PN/8795480 Written by Lesley Gonzales; edited by Vessie Ann Abalos.

*** Intel Assigned Patent for Method and Apparatus for Improving Efficiency of Interrupt Delivery at Runtime in Network System ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,838,864) developed by Yadong Li, Portland, Oregon, and Sujoy Sen, Portland, Oregon, for a "method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system." The patent application was filed on Oct. 23, 2012 (13/657,991). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,838,864.PN.&OS=PN/8,838,864&RS=PN/8,838,864 Written by Deviprasad Jena; edited by Jaya Anand.

*** Intel Assigned Patent ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,838,123) developed by six co-inventors for an "on-demand vacate mechanism for cloud spectrum services." The co-inventors are Bahareh Sadeghi, Portland, Oregon, Srikathyayani Srikanteswara, Portland, Oregon, Carlos Cordeiro, Portland, Oregon, David M. Horne, Chandler, Arizona, Reza Arefi, Great Falls, Virginia, and Geoff O. Weaver, Portland, Oregon.

The patent application was filed on June 26, 2012 (13/533,329). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,838,123.PN.&OS=PN/8,838,123&RS=PN/8,838,123 Written by Sudarshan Harpal; edited by Jaya Anand.

*** Intel Assigned Patent for Projection Interface Techniques ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,839,134) developed by Glen J. Anderson, Beaverton, Oregon, and Subhashini Ganapathy, Portland, Oregon, for projection interface techniques.

The patent application was filed on Dec. 24, 2010 (12/978,533). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=88,39,134.PN.&OS=PN/88,39,134&RS=PN/88,39,134 Written by Sudarshan Harpal; edited by Jaya Anand.

*** Intel Assigned Patent for Apparatus, Method, and System for Implementing Micro Page Tables ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,838,935) developed by 11 co-inventors for an "apparatus, method, and system for implementing micro page tables." The co-inventors are Glenn Hinton, Portland, Oregon, Madhavan Parthasarathy, Portland, Oregon, Rajesh Parthasarathy, Hillsboro, Oregon, Muthukumar Swaminathan, Folsom, California, Raj Ramanujan, Federal Way, Washington, David Zimmerman, El Dorado Hills, California, Larry O. Smith, Beaverton, Oregon, Adrian C. Moga, Portland, Oregon, Scott J. Cape, Portland, Oregon, Wayne A. Downer, Portland, Oregon, and Robert S. Chappell, Portland, Oregon.

The patent application was filed on Sept. 24, 2010 (12/890,585). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,838,935.PN.&OS=PN/8,838,935&RS=PN/8,838,935 Written by Deviprasad Jena; edited by Jaya Anand.

*** Intel Assigned Patent for Method and Apparatus for Tamper Resistant Communication in Virtualization Enabled Platform ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,839,237) developed by Ravi Sahita, Beaverton, Oregon, Uday Savagaonkar, Beaverton, Oregon, and Subhash Gutti, Hillsboro, Oregon, for a "method and apparatus for tamper resistant communication in a virtualization enabled platform." The patent application was filed on Dec. 31, 2007 (11/968,062). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=88,39,237.PN.&OS=PN/88,39,237&RS=PN/88,39,237 Written by Deviprasad Jena; edited by Jaya Anand.

*** Intel Assigned Patent for Systems and Methods for Reducing Power Consumption of Communication Device ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,839,015) developed by Robert Hays, Portland, Oregon, for "systems and methods for reducing power consumption of a communication device." The patent application was filed on Oct. 8, 2012 (13/647,262). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=88,39,015.PN.&OS=PN/88,39,015&RS=PN/88,39,015 Written by Balkishan Dalai; edited by Jaya Anand.

*** Intel Assigned Patent for Masks for Double Patterning Photolithography ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,839,160) developed by Carlos R. Castro-Pareja, Aloha, Oregon, and Allan Xiao Yu Gu, Portland, Oregon, for "masks for double patterning photolithography." The patent application was filed on Dec. 29, 2011 (13/977,630). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=88,39,160.PN.&OS=PN/88,39,160&RS=PN/88,39,160 Written by Sudarshan Harpal; edited by Jaya Anand.

*** Intel Assigned Patent ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,839,450) developed by four co-inventors for a "secure vault service for software components within an execution environment." The co-inventors are David Durham, Beaverton, Oregon, Hormuzd Khosravi, Portland, Oregon, Uri Blumenthal, Fair Lawn, New Jersey, and Men Long, Hillsboro, Oregon.

The patent application was filed on Aug. 2, 2007 (11/833,073). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=88,39,450.PN.&OS=PN/88,39,450&RS=PN/88,39,450 Written by Balkishan Dalai; edited by Jaya Anand.

*** Cypress Semiconductor Assigned Patent ALEXANDRIA, Va., Sept. 17 -- Cypress Semiconductor, San Jose, California, has been assigned a patent (8,838,852) developed by Bert Sullam, Bellevue, Washington, and Haneef Mohammed, Beaverton, Oregon, for a "programmable interrupt routing system." The patent application was filed on March 8, 2012 (13/415,671). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,838,852.PN.&OS=PN/8,838,852&RS=PN/8,838,852 Written by Deviprasad Jena; edited by Jaya Anand.

*** Intel Assigned Patent for Cache Collaboration in Tiled Processor Systems ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,838,915) developed by four co-inventors for "cache collaboration in tiled processor systems." The co-inventors are Ahmad Samih, Beaverton, Oregon, Ren Wang, Portland, Oregon, Christian Maciocco, Portland, Oregon, and Tsung-Yuan C. Tai, Portland, Oregon.

The patent application was filed on June 29, 2012 (13/537,417). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,838,915.PN.&OS=PN/8,838,915&RS=PN/8,838,915 Written by Deviprasad Jena; edited by Jaya Anand.

*** Palo Alto Research Center Assigned Patent ALEXANDRIA, Va., Sept. 17 -- Palo Alto Research Center, Palo Alto, California, has been assigned a patent (8,836,739) developed by five co-inventors for a "method of fabricating low-cost transfix drums for solid ink transfer." The co-inventors are Ashish Pattekar, Cupertino, California, Gregory J. Kovacs, Webster, New York, Paul J. McConville, Webster, New York, James C. Zesch, Santa Cruz, California, and Trevor J. Snyder, Newberg, Oregon.

The patent application was filed on Sept. 7, 2012 (13/607,458). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,836,739.PN.&OS=PN/8,836,739&RS=PN/8,836,739 Written by Kusum Sangma; edited by Jaya Anand.

*** Intel Assigned Patent for Apparatus, System, and Method for Controlling Temperature and Power Supply Voltage Drift in Digital Phase Locked Loop ALEXANDRIA, Va., Sept. 17 -- Intel, Santa Clara, California, has been assigned a patent (8,836,389) developed by Martin Vandepas, Portland, Oregon, for an "apparatus, system, and method for controlling temperature and power supply voltage drift in a digital phase locked loop." The patent application was filed on Sept. 28, 2011 (13/991,614). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,836,389.PN.&OS=PN/8,836,389&RS=PN/8,836,389 Written by Kusum Sangma; edited by Jaya Anand.

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