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United States : IDT Introduces Industry s First Ethernet and IEEE 1588 Timing Devices Optimized for Smart Grid and Industrial Automation Applications [TendersInfo (India)]
[May 06, 2014]

United States : IDT Introduces Industry s First Ethernet and IEEE 1588 Timing Devices Optimized for Smart Grid and Industrial Automation Applications [TendersInfo (India)]

(TendersInfo (India) Via Acquire Media NewsEdge) Integrated Device Technology, Inc., the Analog and Digital Company delivering essential mixed-signal semiconductor solutions, today announced the industry s first Ethernet and IEEE 1588 timing devices optimized to meet the performance, functionality, and cost targets of smart grid and industrial automation applications. The new low-jitter timing products improve the accuracy and reliability of IEEE 1588 time transport and offer important flexibility with an integrated Ethernet digital PLL (DPLL) and digitally-controlled oscillator (DCO) in a single chip.

The 8V89316 and 8V89317 are low-jitter Ethernet PLLs used to frequency synchronize switches and routers via the Ethernet physical layer to improve the reliability and time accuracy of IEEE 1588-based transparent clocks, boundary clocks, and ordinary clocks. The 8V89316 generates clocks suitable for QSGMII (Quad Serial Gigabit Media Independent Interface) and 1 GbE interfaces, while the ultra-low-jitter 8V89317 is suitable for 10 GbE interfaces and adds the ability to lock to 1 PPS (pulse per second) GPS clocks. Both devices include DCOs for increased flexibility, allowing them to lock to an incoming Ethernet clock or synthesize their own IEEE 1588-based clocks that other devices in the system can use as a frequency reference.

IDT s latest Ethernet PLLs lead the market with the combination of performance, features, and cost-effectiveness facilitating the use of Ethernet physical layer clocks in smart-grid and industrial applications, said Louise Gaulin, vice president and general manager of the Network Communications Division at IDT. In addition to best-in-class jitter performance, our combined DPLL and DCO capability offers flexibility to connect an existing electrical timing input, or where that s not feasible, to generate a new one based on IEEE 1588. Major equipment manufacturers are now requiring these levels of performance and functionality because they have been identified as critical factors in time-sensitive applications such as power substation automation.


The 8V89317 can lock to a 1PPS frequency reference from a GPS receiver, allowing use as part of a local network master clock without the need for wire- or fiber-based access to a synchronization source. GPS timing improves flexibility of the physical location of a clock and reduces installation costs for timing islands by eliminating the need to extend a timing network to every location.

The 8V89316 achieves phase jitter below 650 femtoseconds RMS over the 10 kHz to 20 MHz integration range, making it appropriate for 1G Ethernet PHYs and QSGMII (Quad Serial Gigabit Media Independent Interface). The 8V89317 phase jitter is below 300 femtoseconds RMS over the 10 kHz to 20 MHz integration range, capable of meeting the most stringent 10G or 40G Ethernet PHY jitter performance requirements.

(c) 2014 Euclid Infotech Pvt. Ltd. Provided by Syndigate.info, an Albawaba.com company

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