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A High Precision, High PSRR CMOS Bandgap Based on Negative Feedback [Sensors & Transducers (Canada)](Sensors & Transducers (Canada) Via Acquire Media NewsEdge) Abstract: An innovative low temperature coefficient and high power supply rejection bandgap reference (BGR) using double negative feedback and non-linear compensate is described. The circuit uses a negative feedback bandgap core to optimize the temperature coefficient, power supply rejection and line regulation. Simulation results of the proposed BGR implemented in 0.35-um CMOS processing demonstrate that a temperature coefficient of 8.10 ppm/°C is realized at 3.3 V power supply, a power supply ripple rejection radio of -102.7 dB @DC is achieved, and the line regulation is 7.78 µV/V. Copyright © 2013 IFSA. Keywords: Bandgap reference, Negative feedback, Temperature compensation. (ProQuest: ... denotes formulae omitted.) 1. Introduction Precision voltage references independent of temperature and supply play an important role in ADC, DAC and LDO circuits. The temperature coefficient (TC) and power supply rejection ratio (PSR) as two key factors define the performance of the reference. So it is necessary to design a low TC and high PSR reference. Conventional bandgap reference (BGR) is first order temperature compensated. With regards to the non-linear of emitter-base voltage of bipolar junction transistor (BJT), the TC of conventional Bandgap Reference Circuit (BGR) is always limited between 20-100 ppm/°C [1,2]. In order to canceling this nonlinear component, the classical method is through the addition of a second-order or high-order PTAT term to the output voltage, which is denoted as curvature-corrected bandgap references [3]. In theory, T ln(T) correction is the best way to compensate the nonlinearity of Vbe . However, it is quite difficult to realize such relationship in reality. Most of the curvature-corrected BGR use a proximate way to eliminate the nonlinearity [4]. A piecewise nonlinear squared-PTAT current flowing through MOSFET is added to the first-order BGR to compensate the nonlinear Vbe in high temperature [5] Or Vbe could replaced by a complementary-toabsolute temperature current, the circuits uses PTAT and CTAT to implement the second-order curvaturecompensation [6]. Instead of second-order compensation technique, a class of exponential and logarithmic curvature compensation is used to decrease the temperature drift in whole temperature range and achieve 5 ppm/°C [1,7]. To improving PSRR, a self-biased symmetrically matched current-voltage mirror is presented to enhance the PSRR to around -50 dB with 0.35 pm CMOS process [4]. Two negative feedback loops to achieve -80 dB PSR performance with TSMC 0.35 pm CMOS process, which are the pre-regulator of line voltage and a negative feedback loop in the bandgap core [7]. In this paper, new circuit architecture is proposed to improve a BGR's TC as well as the PSRR. The circuit utilizes a negative feedback in a first-order voltage reference [8] for curvature-corrected compensation and high PSRR. The principle of classic bandgap references is introduced in Section 2. Section 3 analyses the improved bandgap reference in detail. Simulated results as well as performance comparison with some other reported bandgap references in recent years are presented in Section 4. And the conclusion is given in Section 5. 2. Principle of Classic BGR Fig. 1 shows the classic structure circuit of BGR [7]. The feedback loop constructed by P\-Pi and N\ - AG forces the voltage Va = Vb , the current of R\ is ...(1) where Vbe means the emitter-base voltage of bipolar junction transistor, Vt represents the thermal voltage and M is the emitter area ratio of Q\ and Qi. N means that Pi mirrors N times current of P\ or Pi, so the output voltage is ...(2) However the relationship between temperature and emitter-base voltage of PNP BJTs, which are biased in forward active region, can be expressed as [3]: ... (3) where Vgo is the bandgap voltage of silicon extrapolated at 0 K, To is the reference temperature, k is the Boltzmann 's constant, ri is the temperature constant depending on the technology, m is the order of the temperature. At room temperature ôVebiI dT »-1.5m F / °K and dVr/dT= k / q « O.OSlmV/°K [10], q is the electronic charge. By properly setting resistance values of R\ and R2, the (2) will be independent of the temperature. However, due to the non-linear of Veb , the temperature coefficient of Vref will not always is zero. 3. Design of Proposed BGR Fig. 2 shows the proposed bandgap reference circuit, and the deviations from the original design are highlighted. The BGR is consist of regulation voltage generate block, reference voltage generate block, PSRR enhanced block and start-up block four parts. 3.1. Temperature Coefficient Analysis As the reference voltage generate block shows in Fig. 2, P\-P2 and Ah-AG form a 1:1 current mirror circuit [4] which forces Im = Ini = I and Vb = Va = Veb2 .Then the relationship between current and voltage of Ri is ...(4) Assume that the current of Pi is N times that of P\ and P2, the emitter area ratio of Q\ and Q2 is M, the equations about emitter-base voltage of Qx and Q2 can be obtained ...(5) Substitute (5) into (4) is ...(6) Assuming the transconductance of Ni is gmNi, the equation (6) can be simplified as ...(7) If condition that gmNiVref -C 7 can be satisfied, (7) can be expand in Taylor series as ...(8) To obtains the relationship between the current and the temperature. The partial derivative of (8) equation with respect to the temperature as shown below ...(9) Suppose dVREF I dT * 0, as the condition gmNíVREF I is satisfied, proper value of R\ can be chosen to meet ...(10) ...(11) The relationship ... can be met easily, so the current I shows a positive correlation to temperature. And in Fig. 2 the output reference voltage Vref can be expressed as ...(12) Taking partial derivative of (12) with respect to the temperature, expression can be got as ...(13) The first term in (13) can be transformed as ...(14) Obviously, the expression gmmVREF <C I(N +1) was met before, (14) can be approximately to that ...(15) The first term in (15) can acquire from [9]. With (15), (13) can be rewritten as ...(16) The (10) requires a large and appropriate value of Ri, so the expression (9) can be satisfied simply. ...(17) The (17) can achieve d(Vr /1) / dT > 0, which indicates that Vt i I is also a positive correlation to temperature. Analyze the (16) in detail. First observing the numerator of (16), the first and second terms represent the negative temperature coefficient and the third and forth terms stand for the positive temperature coefficient. Supposed that right parameter is chosen to let the numerator of (16) is zero correspond to the temperature To. When the temperature is rising, the first term becomes more negative to lead (16) to be minus. However, the second term becomes less negative at the moment to relive the change of (16) as well as the third and forth terms become more positive. Proper value of each component will make the tendency of changes of negative and positive temperature coefficient compensate each other to achieve a low TC of the BGR. As well as the temperature is falling. Even the numerator of (16) is nonzero, the denominator is going to become larger which make the entity value of (16) reduce when the temperature is rising. But it may have an exactly opposite effect when the temperature drops. Fortunately, in most cases the chip works in a high temperature environment. 3.2 PSRR Analysis Besides the self-biasing technique, the band gap circuit operates from an internal supply Vreg , which regulating the supply voltage to the BGR through Loopl in the PSRR enhanced block. In Fig. 2, there is another negative feedback loops in the reference voltage generate block brought by Ni. So the PSRR of the bandgap voltage Vref / Vdd output can be written as ... (18) PSRRl represents the supply rejection of line regulation Vref /Vdd, and PSRR2 represents the supply rejection of the bandgap core. In Loopl, the Vreg is adjusted by means of a high gain feedback loop. The voltage variation between is sensed by two stage amplifier made Ps- 6 and AG-6. The amplified voltage is then converted to current by N6, which feeds a current into the node Vreg so as to force it to the right voltage. For simplicity, the influence of Ni is omitted, then the loop-gain on node Vreg can be expressed by ... (19) where A\ is the open-gain, ß\ is the feedback factor, rc is the equivalent impedance of node C, rase is the equivalent impedance of node Vreg , and rou is the output impedance of the component u , where u represents N\ and Q\. In addition, assume that the impact factor from Vdd to Vreg is k\, which can be expressed by ...(20) where A Vdd is the variation of Vdd . According to Fig. 3, and the two equations, (19) and (20), the variation of Vreg can be expressed as ...(21) ...(22) Concluded in [2], The higher the loop gain, the higher will be the rejection of the variations of Vreg . The PSRRl of the output reference voltage will be increase with the addition of the amplifier gain, but high gain increases the requirement for designing and may also cause the stability problem. The use of AG reduces that requirement and relieves the problem. In Loop2, the node voltage variation of Vref is eliminated by Ni. The variation in Vreg is sensed by the MOSFET Ni and then transformed to the compensation current which goes through Q2. This current leads the emitter-base voltage VEB2 to offset the variation in the node VREF . Similarly, suppose that the impact factor from VREG to VREF is k2, which means that ...(23) the current variation of N3 is given by (23) ... ... (24) where gmN3 is the transconductance of A3, which is gmN3 = ß(VREF - VTHN). At the same time, the current through Q1 changes ... (25) where req represents the equivalent impedance of this branch, which is ... (26) Using (24)-(26), the current variation of Q2 can be expressed as ... (27) On the basis of the exponentially relationship of diodes [5], we can make an approximate treatment to get that ... (28) Combining (27) and (28) yields ... (29) Because VREF = VEB2 + A * IR2, the relationship between AVEB 2 and A VREF is AVEB2 = AVREF - ?I . NR2. We will have the loopgain of node Vref through (25) and (29) as ... (30) Similar to (22), equation to express PSRR of node Vref to Vreg can be given by ... (31) According to (22) and (31), the PSRR of node Vref to Vdd can be expressed as ... (i+A4Xi+Ä4) (32) where ß1 A1 and ß2 A2 are given in (19) and (30) respectively. From (32), we can find that A3 brings the terms 1 / (1 + ß2 A2) which improves the PSRR of the output reference voltage substantially and reduces the high requirement for the two stage amplifier, and if gmN3 becomes larger, the PSRR of node Vref will becomes better in theory. 3.3. Start-up Analysis The start-up block of the proposed BGR comprises of Pu and A9-12 in Fig. 2. At the first the PMOSP11 will be on because of the Vreg = 0 in the beginning, the voltage of node D is pulled up by Vdd , then An - An will be turn on finally, Vdd can charges node Vreg, and meanwhile A10 guarantees the gate voltage of Pi-2 is low. The voltage of node Vreg could be pulled up and then make Pi-2 open. The whole circuit turns on. Therefore, the proposed BGR is driven towards the desired stable state. P11 can be turned off when the voltage at node Vref exceeds some amount, and A10 - A12 will be off due to the voltage at node D is pulled down by A9. Thus the start-up circuit will not affect the normal operation of the proposed BGR. 4. Simulation Results The proposed BGR shown in Fig. 2 has been implemented in 0.35 um CMOS technology. However (17) and (32) decide TC and PSRR respectively are both difficult to find the proper parameters of each component. SO their common factor gmN3 is an important which is decided by the W / L of A3 and its DC operating point. So we could use the computer to find the proper size of A3 after design other components roughly first. Fix the W of A3 as 500 nm, we can get the TC-L and PSRR - L curve in Fig. 4. Fig. 4 shows that the TC of the proposed BGR will get the optimal solution when the L of A3 varies and the PSRR will get worse with the L is being stretched. When the L of A3 is 9.7 pm, the TC is 8.2 ppm/°C and PSRR is 102.7 dB. Fig. 5 shows the difference of TC between the firstorder conventional bandgap and the proposed BGR measured with the operating temperatures varying from -45 °C to 135 °C. The TC of the first order BGR is 8.76 ppm/°C over a range from -40 °C to -85 °C, and 131.53 ppm/°C over a range from -45 °C to 135 °C. The reference voltage of the proposed BGR is 1.196 V with a TC of only 8.10 ppm/°C at -40 °C to 125 °C. Fig. 6 shows the conventional BGR owns a - 69.23 dB @DC, and -66.85 dB @1 KHz while the proposed BGR achieves -102.7 dB @DC, -102.7 dB @1 KHz and even -81.5 dB @1 Mhz. Fig. 7 shows the difference of line regulation (LNR) between conventional BGR and the BGR of this work. The results show that the BGR of this work reaches 7.78 pV/V but the conventional BGR gets 370 pV/V with Vdd ranging from 3.0 V to 3.6 V. Table 1 summarizes a Brief comparison onto the results of the proposed BGR in this paper and the conventional BGR to show the improvements from the conventional structure. Table 2 compares some recently published reference circuits with the proposed BGR in this paper. From the comparison, we can see that the structure of the voltage reference proposed by this paper is brief, which is only added a single NMOS based on the conventional structure, with regard to other curvature compensation structure [1, 4-7]. And the circuit of this work also owns good temperature characteristics over -40 °C-125 °C, and excellent PSRR performance at the range of DC-1 MHz. Conclusion An innovative low TC and high PSR BGR has been proposed and implemented by 0.35 um/3.3 V CMOS technology in this paper. High-order temperature compensated and PSR enhanced are both achieved by a negative feedback in bandgap core circuit. A thorough analysis of the proposed curvature corrected BGR architecture, along with the simulation results is presented. Simulation results using Spectre of Cadence show that the average output voltage is 1.196 V with a 8.1 ppm/°C temperature coefficient and a high PSRR which is - 102.7 dB @DC, -102.7 dB @1 KHz and -81.5 dB @1 MHz. The high-performance of the proposed BGR provides a competitive advantage in the market. References [1] . Ze-Kun Zhou, Yue Shi, Zhi Huang, et al,. A 1.6 V 25 uA 5 ppm/°C Curvature-Compensated Bandgap Reference, IEEE Journals & Magazines, Vol. 59, Issue 4, 2012, pp. 677-684. [2] . P. E. Allen, D. R. Holberg, CMOS analog circuit design, 2nd Edition, Publishing House of Electronics Industry, Beijing, 2003, pp. 125-130. [3] . Rincon-Mora, Voltage references from diodes to precision high-order bandgap circuits, Wiley-IEEE, 2002, pp. 79-118. [4] . Yat-Hei Lam, Wing-Hung Ki, CMOS bandgap references with self-biased symmetrically matched current-voltage mirror and extension of sub-1-V design, IEEE Journals & Magazines, Vol. 18, Issue 6,2010, pp. 857-865. [5] . Ruhaifi Abdullah Zawawi, Othman Sidek, Wan Mohd Hafizi Wan Hassin, et al., An improvement of a piecewise curvature-corrected CMOS bandgap reference, IEICE Electronics Express, Vol. 8, Issue 22,201 l,pp. 1876-1881. [6]- Chuan Zhang, Shuzhuan He, Ying Zhu, et al., A high precision CMOS bandgap reference with secondorder curvature-compensation, in Proceedings of the IEEE 7th International Conference (ASICON' 07), 2007, pp. 553-556. [7]- Ning Zhi-Hua, He Le-Nian, Wang Yi, et al., A novel high PSR voltage reference with secondary temperature compensation, in Proceedings of the IEEE International Conference on Electrical and Control Engineering (ICECE), Wuhan, 25-27 June 2010, pp. 3200-3203. [8.} Rincon-Mora, Voltage references from diodes to precision high-order bandgap circuits, Wiley-IEEE, 2002, pp. 79-118. [9.] Behzad Razavi, Design of analog CMOS integrated circuits, Xi'an Jiaotiong University Press, Xi'an, 2002, pp. 309-327. Lin CHUN, Lin YU, Zhang WEICHEN, Chen XIURONG, Li XIAOCHAO Department of Electrical Engineering, Xiamen University, Xiamen, Fujian of China E-mail: [email protected], [email protected] Received: 11 September 2013 /Accepted: 22 November 2013 /Published: 30 December 2013 (c) 2013 International Frequency Sensor Association |