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U.S. Patents Awarded to Inventors in Texas (June 19)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., June 19 -- The following federal patents were awarded to inventors in Texas. *** United Services Automobile Association Assigned Patent ALEXANDRIA, Va., June 19 -- United Services Automobile Association, San Antonio, has been assigned a patent (8,468,086) developed by Robert Dibble, Fair Oaks Ranch, Texas, for a "system and method for protecting a debt." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Disclosed are systems and methods for protecting a debt. The systems and methods provide techniques for providing a set-amount loan to a customer, collecting a premium payment for the protection of a debt associated with the set-amount loan, receiving information about a debt excusing event that has occurred to the customer, and terminating at least a portion of the debt associated with the set-amount loan." The patent application was filed on Oct. 11, 2006 (11/548,448). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,68,086.PN.&OS=PN/84,68,086&RS=PN/84,68,086 Written by Amal Ahmed; edited by Jaya Anand. *** International Business Machines Assigned Patent for Data Element Categorization in a Service-oriented Architecture ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,159) developed by six co-inventors for a "data element categorization in a service-oriented architecture." The co-inventors are Faried Abrahams, Laytonsville, Md., Ali P. Arsanjani, Fairfield, Iowa, Kerard R. Hogg, Victoria, Australia, Ahamed Jalaldeen, Karnataka, India, Siddharth Purohit, Allen, Texas, and Gandhi Sivakumar, Melbourne, Australia. The abstract of the patent published by the U.S. Patent and Trademark Office states: "An approach is presented for specifying categories of data elements during a service specification phase of a service-oriented architecture (SOA) life cycle defined in a service modeling methodology like Service-Oriented Modeling and Architecture (SOMA). A Unified Modeling Language based SOA modeling tool for the service modeling methodology includes a middleware based integration plug-in that categorizes service-specific data elements as transaction elements, glue elements, core Common Information Model (CIM) elements, and elements extending the CIM elements, and associates the categorized data elements with corresponding operations of the service being modeled." The patent application was filed on Aug. 24, 2012 (13/593,596). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,68,159.PN.&OS=PN/84,68,159&RS=PN/84,68,159 Written by Amal Ahmed; edited by Jaya Anand. *** Qxzeb Assigned Patent ALEXANDRIA, Va., June 19 -- Qxzeb, Longview, Texas, has been assigned a patent (8,468,369) developed by Mark Nair, Amarillo, Texas, for a "system, method and apparatus for controlling the dissemination of digital works." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system, business methodology and apparatus for facilitating controlled dissemination of digital works is disclosed. An audio and video organizer, entertainment, and communication unit that plays back audio and video media content received from a central storage server. The unit relies on a smartcard, which has a personalized key that unlocks encrypted content. Using the unit, a user can purchase music or other types of media using an appropriate ordering method. The central storage server then transmits a double-encrypted, compressed audio file to the unit, where it is decrypted based on the smartcard key, and available for listening." The patent application was filed on April 12, 2011 (13/066,314). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,369.PN.&OS=PN/8,468,369&RS=PN/8,468,369 Written by Kusum Sangma; edited by Anand Kumar. *** FutureWei Technologies Assigned Patent ALEXANDRIA, Va., June 19 -- FutureWei Technologies, Plano, Texas, has been assigned a patent (8,468,343) developed by Tie Liu, College Station, Texas, and Yufei Blankenship, Kildeer, Ill., for a "system and method for securing wireless transmissions." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for securing wireless transmissions is provided. A method for transmitting secure messages includes selecting a bin of codewords from a plurality of bins. The bin of codewords containing a plurality of sub-bins of codewords, and the selecting is based on a first message. The method also includes selecting a sub-bin of codewords from the plurality of sub-bins of codewords based on a second message, selecting a codeword from the sub-bin of codewords, and transmitting the selected codeword to a legitimate receiver." The patent application was filed on Jan. 13, 2010 (12/686,995). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,343.PN.&OS=PN/8,468,343&RS=PN/8,468,343 Written by Kusum Sangma; edited by Anand Kumar. *** University of South Carolina Assigned Patent ALEXANDRIA, Va., June 19 -- The University of South Carolina, Columbia, S.C., has been assigned a patent (8,468,355) developed by John H. Gerdes Jr., Cayce, S.C., Joakim Kalvenes, Dallas, and Chin-Tser Huang, Irmo, S.C., for a "multi-dimensional credentialing using veiled certificates." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In accordance with certain embodiments of the present disclosure, a method for creating a veiled certificate is provided. The method comprises requesting a certificate from a regulator by sending a message with a digital signature of the message signed by the owner. The message comprises an owner's veiled certificate token, the veiled certificate token comprising an encrypted version of the owner's identification data and the owner's identification public key for the certificate. The message further comprises the identification public key, the whole message being encrypted using the regulator's external public key. The certificate request is validated by verifying the sender's identity through validation of the digital signature using the owner's external public key and verifying the veiled certificate token using the individual' external public key. A veiled certificate is created by combining the veiled certificate token, identification public key and digitally signing the veiled certificate with the regulator's private key, wherein the owner's identification information is inaccessible from the veiled certificate, except to the certificate owner." The patent application was filed on Dec. 21, 2009 (12/643,364). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,355.PN.&OS=PN/8,468,355&RS=PN/8,468,355 Written by Kusum Sangma; edited by Anand Kumar. *** Texas Instruments Assigned Patent ALEXANDRIA, Va., June 19 -- Texas Instruments, Dallas, has been assigned a patent (8,468,406) developed by Lee D. Whetsel, Parker, Texas, for an "access port selector and gating selecting test access port." The abstract of the patent published by the U.S. Patent and Trademark Office states: "The disclosure describes a novel method and apparatuses for allowing a controller to select and access different types of access ports in a device. The selecting and accessing of the access ports is achieved using only the dedicated TDI, TMS, TCK, and TDO signal terminals of the device. The selecting and accessing of device access ports can be achieved when a single device is connected to the controller, when multiple devices are placed in a daisy-chain arrangement and connected to the controller, or when multiple devices are placed in a addressable parallel arrangement and connected to the controller. Additional embodiments are also provided and described in the disclosure." The patent application was filed on Sept. 27, 2012 (13/628,802). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,406.PN.&OS=PN/8,468,406&RS=PN/8,468,406 Written by Kusum Sangma; edited by Anand Kumar. *** Bank of America Assigned Patent ALEXANDRIA, Va., June 19 -- Bank of America, Charlotte, N.C., has been assigned a patent (8,468,069) developed by Joseph Michael Stinson, Arlington, Texas, for an "automatic modification of financial record parameters." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Formatting of data entered and/or stored in a financial transaction record may be automatically corrected or modified to an expected or compatible format. The format in which data is to be stored may be defined by a financial institution processing the transaction and/or a customer affected by the transaction. Format rules may be defined and used to judge whether a transaction record parameter meets the required format. If so, the record parameter may be validated and saved. If, however, the parameter is not formatted according to the rule, the system may automatically revise the value stored in the parameter to satisfy the requirements. According to another aspect, if a transaction record has been modified, manual confirmation of the change may be requested." The patent application was filed on Jan. 27, 2010 (12/694,618). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,68,069.PN.&OS=PN/84,68,069&RS=PN/84,68,069 Written by Amal Ahmed; edited by Jaya Anand. *** Texas Instruments Assigned Patent for Data Register Control from TAP+ATC or Discrete WSP Signals ALEXANDRIA, Va., June 19 -- Texas Instruments, Dallas, has been assigned a patent (8,468,403) developed by Lee D. Whetsel, Parker, Texas, for a "data register control from TAP+ATC or discrete WSP signals." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In a first embodiment a Test Access Port (TAP) of IEEE standard 1149.1 is allowed to commandeer control from a Wrapper Serial Port (WSP) of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC (Auxiliary Test Control bus) or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals." The patent application was filed on March 2, 2012 (13/411,124). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,403.PN.&OS=PN/8,468,403&RS=PN/8,468,403 Written by Kusum Sangma; edited by Anand Kumar. *** Dell Products Assigned Patent ALEXANDRIA, Va., June 19 -- Dell Products, Round Rock, Texas, has been assigned a patent (8,468,139) developed by Clint H. O'Connor, Austin, Texas, Michael Haze, Round Rock, Texas, and Yuan-Chang Lo, Austin, Texas, for an "acceleration of cloud-based migration/backup through pre-population." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system, method, and computer-readable medium are disclosed for performing automated, cloud-based migrations of entitled digital assets. A set of entitlement data corresponding to a set of digital assets installed on a first system is processed with a set of digital asset source data to generate an equivalent set of digital assets. A first identifier associated with the source system is then cross-referenced to a second identifier associated with a target system. The second identifier and the set of entitlement data are processed to generate a second set of digital asset entitlements entitling the target system to use the set of equivalent digital assets. A migration request and the second identifier are then processed to provide the set of equivalent digital assets to the target system." The patent application was filed on July 16, 2012 (13/549,982). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,68,139.PN.&OS=PN/84,68,139&RS=PN/84,68,139 Written by Amal Ahmed; edited by Jaya Anand. *** Oracle International Assigned Patent ALEXANDRIA, Va., June 19 -- Oracle International, Redwood City, Calif., has been assigned a patent (8,468,425) developed by Paul J. Jordan, Austin, Texas, and Christopher H. Olson, Austin, Texas, for a "register error correction of speculative data in an out-of-order processor." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit." The patent application was filed on Nov. 14, 2011 (13/295,554). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,425.PN.&OS=PN/8,468,425&RS=PN/8,468,425 Written by Kusum Sangma; edited by Anand Kumar. *** Dell Products Assigned Patent for System and Method for Providing Access to an Information Handling System ALEXANDRIA, Va., June 19 -- Dell Products, Round Rock, Texas, has been assigned a patent (8,468,362) developed by David Konetski, Austin, Texas, and Frank H. Molsberry, Georgetown, Texas, for a "system and method for providing access to an information handling system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An information handling system includes a memory and a detector circuit. The memory is configured to store a first electrocardiogram measurement. The detector circuit is configured to receive a second electrocardiogram measurement in response to a specific combination of keys of a keyboard being pressed for a specific period of time, wherein each key in the specific key combination includes an electrocardiogram sensor on a top surface of the key, to authorize a user and log the user onto the information handling system when the second electrocardiogram measurement matches the first electrocardiogram measurement, and otherwise: to deny access to the information handling system; to increase a counter; to determine whether the counter has exceeded a threshold; and to request that an input window is displayed when the counter has exceeded the threshold." The patent application was filed on June 3, 2011 (13/152,470). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,362.PN.&OS=PN/8,468,362&RS=PN/8,468,362 Written by Kusum Sangma; edited by Anand Kumar. *** Dell Products Assigned Patent ALEXANDRIA, Va., June 19 -- Dell Products, Round Rock, Texas, has been assigned a patent (8,468,380) developed by Ashish Munjal, Round Rock, Texas, Alan Brumley, Cedar Park, Texas, and Jaydev Reddy, Austin, Texas, for a "power consumption monitor and method therefor." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A power supply unit of an information handling system determines that a power consumption module of the information handling system is available. If the power consumption module is available, the power supply unit measures input power of the power supply unit and provides a representation of the input power to the power consumption module in response to receiving a power measurement request from the power consumption module. If the power supply unit determines that the power consumption module is not available, the power supply unit measures input power of the power supply unit and stores a representation of the input power at the power supply unit independent of a power measurement request from the power consumption module." The patent application was filed on July 31, 2009 (12/533,905). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,380.PN.&OS=PN/8,468,380&RS=PN/8,468,380 Written by Kusum Sangma; edited by Anand Kumar. *** International Business Machines Assigned Patent ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,607) developed by Messaoud Benantar, Austin, Texas, Patrick M. Commarford, Louisville, Ky., and Ajay R. Karkala, Austin, Texas, for "associating multiple security domains to application servers." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Multiple security domains can be created and associated with various scopes within the cell allowing security configurations of each scope to be managed collectively. Examples of scopes include the entire cell, one or more application servers, one or more applications, one or more clusters, one or more service integration buses, one or more nodes, etc. Security configurations associated with the security domains can be applied to the scopes based on a hierarchy of the security domains. In addition, new security domains may be created automatically based on security requirements of newly installed applications." The patent application was filed on Oct. 7, 2009 (12/574,825). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,607&OS=8,468,607&RS=8,468,607 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Predicting and Avoiding Operand-store-compare Hazards in Out-of-order Microprocessors ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,325) developed by eight co-inventors for "predicting and avoiding operand-store-compare hazards in out-of-order microprocessors." The co-inventors are Gregory W. Alexander, Pflugerville, Texas, Khary J. Alexander, Poughkeepsie, N.Y., Brian Curran, Saugerties, N.Y., Jonathan T. Hsieh, Vernon, Conn., Christian Jacobi, Poughkeepsie, N.Y., James R. Mitchell, Poughkeepsie, N.Y., Brian R. Prasky, Poughkeepsie, N.Y., and Brian W. Thompto, Austin, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag." The patent application was filed on Dec. 22, 2009 (12/644,923). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,325.PN.&OS=PN/8,468,325&RS=PN/8,468,325 Written by Kusum Sangma; edited by Anand Kumar. *** AT&T Intellectual Property I Assigned Patent for Mobile Devices Having Plurality of Virtual Interfaces ALEXANDRIA, Va., June 19 -- AT&T Intellectual Property I, Atlanta, has been assigned a patent (8,468,550) developed by Larry B. Pearson, San Antonio, for "mobile devices having plurality of virtual interfaces." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Mobile devices, systems and methods are described with a plurality of virtual machines, wherein each virtual machine executes a separate virtual interface, or guest operating system. Each guest operating system corresponds to a different virtual device having its own contact list, applications, and so on. A virtual "device" can be controlled by an employer or service provider, and is a secure space that provides authenticated applications that are walled off from another virtual device. A host operating system provides a hardware abstraction layer. A proxy server on the host operating system receives an incoming signal from a remote device on the external network, and routes the incoming signal to one of the first and second virtual machines based on a call context. A method and computer program product for providing a plurality of virtual interfaces on a mobile device are also disclosed." The patent application was filed on June 18, 2010 (12/818,923). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,550&OS=8,468,550&RS=8,468,550 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Restoring Programs After Operating System Failure ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,388) developed by Kulvir S. Bhogal, Pflugerville, Texas, William Griffith, Austin, Texas, and Mark W. Talbot, Austin, Texas, for "restoring programs after operating system failure." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A state restoration unit tracks opening and closing of programs within a computer operating system. Responsive to detecting opening and closing of programs, a state restoration structure is updated. After the computer operating system restarts from a failure, the state restoration structure is accessed. The state restoration unit restores those of the programs indicated as open in the state restoration structure." The patent application was filed on April 20, 2010 (12/763,735). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,388.PN.&OS=PN/8,468,388&RS=PN/8,468,388 Written by Kusum Sangma; edited by Anand Kumar. *** International Business Machines Assigned Patent for Facilitating Data Compression During Replication Using a Compressible Configuration Bit ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,315) developed by four co-inventors for a "facilitating data compression during replication using a compressible configuration bit." The co-inventors are Michael E. Browne, Staatsburg, N.Y., Nancy J. Finn, Stormville, N.Y., Christina Lara, Tucson, Ariz., and Maria R. Ward, Pflugerville, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Computer program product, system and method are provided for facilitating data replication in a storage system. A logical volume of a first storage array of a replicated pair is preconfigured with one or more logical volume attributes, which include a compressible configuration bit that indicates whether data blocks to be stored to that logical volume are compressible during replication. Subsequently, with receipt of a data block at the first storage array to be stored to the logical volume, a check of the compressible configuration bit is made to determine whether the data block is compressible during replication, and if so, the data block is compressed for replication. The compressible configuration bit is placed into the payload region of the data packet being replicated to the second storage array. At the second storage array, the compressible configuration bit is used to determine whether to uncompress the replicated data block." The patent application was filed on Oct. 28, 2009 (12/607,118). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,468,315.PN.&OS=PN/8,468,315&RS=PN/8,468,315 Written by Kusum Sangma; edited by Anand Kumar. *** Raytheon Assigned Patent for System and Method for Host-level Malware Detection ALEXANDRIA, Va., June 19 -- Raytheon, Waltham, Mass., has been assigned a patent (8,468,602) developed by six co-inventors for a "system and method for host-level malware detection." The co-inventors are Monty D. McDougal, Plano, Texas, Brian N. Smith, Richardson, Texas, Keven K. Kalkbrenner, Dallas, Bradley T. Ford, Wylie, Texas, Randy S. Jennings, Plano, Texas, and William E. Sterns, Wylie, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "According to one embodiment, a computer-implemented method includes: accessing a set of configuration parameters, accessing a set of identifiers of files known not to be malware, and accessing a set of identifiers of files known to be malware. Further, the method includes: comparing a first file to the set of configuration parameters, determining that a first hash of the first file is not in the set of identifiers of files known not to be malware and that the first hash is not in the set of identifiers of files known to be malware, and sending the at least one file and information related to the at least one file to be analyzed for malware. The method includes deleting the set of configuration parameters, the set of identifiers of files known not to be malware, and the set of identifiers of files known to be malware after sending the first file." The patent application was filed on March 8, 2010 (12/719,614). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,602&OS=8,468,602&RS=8,468,602 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,306) developed by seven co-inventors for a "microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions." The co-inventors are Aaron Tsai, Poughkeepsie, N.Y., Barry W. Krumm, Poughkeepsie, N.Y., James R. Mitchell, Poughkeepsie, N.Y., Bradley Nelson, Austin, Texas, Brian D. Barrick, Pflugerville, Texas, Chung-Lung Kevin Shum, Wappingers Falls, N.Y., and Michael H. Wood, Poughkeepsie, N.Y. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request." The patent application was filed on Feb. 15, 2008 (12/031,858). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,306&OS=8,468,306&RS=8,468,306 Written by Arpi Sharma; edited by Anand Kumar. *** International Business Machines Assigned Patent for Logic Modification Synthesis for High Performance Circuits ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,477) developed by Haoxing Ren, Austin, Texas, for a "logic modification synthesis for high performance circuits." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for IC modification is disclosed. The method recognizes an original HDL file prescribing an original logic, an original netlist incorporating the original logic, and a new HDL file prescribing a new logic. The new logic comprises desired logic changes relative to the original logic. If a signal is different between the new HDL file and the original HDL file the method adds a user hint to both the original HDL file and the new HDL file. Using the original HDL file, the original netlist, the new HDL file, and the user hints, the method synthesizes a delta netlist for inserting into the original netlist, whereupon this insertion the original netlist will incorporate the new logic." The patent application was filed on April 28, 2011 (13/096,361). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,477&OS=8,468,477&RS=8,468,477 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Adjusting CPU Time Allocated to Next Thread Based on Gathered Data in Heterogeneous Processor System Having Plurality of Different Instruction Set Architectures ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,532) developed by four co-inventors for an "adjusting CPU time allocated to next thread based on gathered data in heterogeneous processor system having plurality of different instruction set architectures." The co-inventors are Maximino Aguilar Jr., Georgetown, Texas, David John Erb, Austin, Texas, Sidney James Manning, Austin, Texas, and James Michael Stafford, Round Rock, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method that optimizes system performance using performance monitors is presented. The method gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread." The patent application was filed on June 21, 2006 (11/425,448). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,532&OS=8,468,532&RS=8,468,532 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Raytheon Assigned Patent ALEXANDRIA, Va., June 19 -- Raytheon, Waltham, Mass., has been assigned a patent (RE44,303) developed by five co-inventors for a "passivation layer for a circuit device and method of manufacture." The co-inventors are John Bedinger, Garland, Texas, Michael A. Moore, Fort Worth, Texas, Robert B. Hallock, Newton, N.H., Kamal Tabatabaie, Sharon, Mass., and Thomas E. Kazior, Sudbury, Mass. The abstract of the patent published by the U.S. Patent and Trademark Office states: "According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter.sup.2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 10.sup.15 ohm-centimeter, and a defect density less than 0.5/centimeter.sup.2." The patent application was filed on Aug. 2, 2012 (13/565,302). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=RE44,303&OS=RE44,303&RS=RE44,303 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Hypervisor-based Data Transfer ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,551) developed by five co-inventors for a hypervisor-based data transfer. The co-inventors are Kavitha Vittal Murthy Baratakke, Round Rock, Texas, Pramod Achyut Bhandiwad, Bangalore, India, Nikhil Hegde, Austin, Texas, Sivakumar Krishnasamy, Bangalore, India, and G. Shantala, Bangalore, India. The abstract of the patent published by the U.S. Patent and Trademark Office states: "In a computer system having memory, at least one processor and a physical input-output adapter, the at least one processor generates logical partitions, including local logical partitions and an input-output logical partition. The logical partitions have respective local virtual adapters. The input-output logical partition has a shared virtual adapter configured to communicate with the physical input-output adapter, such that a plurality of the local logical partitions share the physical input-output adapter via the shared virtual adapter. The at least one processor provides communication for ones of the local virtual adapters of the local logical partitions directly with the physical input-output adapter by a hypervisor." The patent application was filed on June 30, 2010 (12/827,741). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,551&OS=8,468,551&RS=8,468,551 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Dell Products Assigned Patent ALEXANDRIA, Va., June 19 -- Dell Products, Round Rock, Texas, has been assigned a patent (8,468,295) developed by Stuart Allen Berke, Austin, Texas, and William Sauber, Georgetown, Texas, for a "system and method for reducing power consumption of memory." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable." The patent application was filed on Dec. 2, 2009 (12/629,681). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,295&OS=8,468,295&RS=8,468,295 Written by Arpi Sharma; edited by Anand Kumar. *** Intel Assigned Patent ALEXANDRIA, Va., June 19 -- Intel, Santa Clara, Calif., has been assigned a patent (8,468,309) developed by four co-inventors for an "optimized ring protocols and techniques." The co-inventors are Meenakshisundaram R. Chinthamani, Hillsboro, Ore., R. Guru Prasadh, Austin, Texas, Hari K. Nagpal, Southborough, Mass., and Phanindra K. Mannava, Folsom, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed." The patent application was filed on Sept. 25, 2010 (12/890,650). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,309&OS=8,468,309&RS=8,468,309 Written by Arpi Sharma; edited by Anand Kumar. *** International Business Machines Assigned Patent for Method for Efficient Guest Operating System (OS) Migration Over a Network ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,288) developed by five co-inventors for a "method for efficient guest operating system (OS) migration over a network." The co-inventors are Kevin M. Corry, Austin, Texas, Mark A. Peloquin, Austin, Texas, Steven L. Pratt, Austin, Texas, Karl M. Rister, Austin, Texas, and Andrew M. Theurer, Austin, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method, data processing system and computer program product enables efficient transfer of a virtual machine from a first data processing system (DPS) to a second DPS using a combination of Transmission Control Protocol (TCP) and Uniform Data Protocol (UDP). A virtual machine migration (VMM) utility identifies all memory pages of the first virtual machine. The VMM utility notifies the second DPS via TCP of the scheduled transfer of the virtual machine. The VMM utility copies and transfers the memory pages of the virtual machine to the second DPS via UDP. When all expected components of the virtual machine are not received by the second DPS and/or memory data is modified within the memory pages during the migration, the VMM utility combines the missing data and the modified data and transfers the final components of the virtual machine using TCP. Execution of the virtual machine resumes on the second DPS." The patent application was filed on Dec. 10, 2009 (12/634,830). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,288&OS=8,468,288&RS=8,468,288 Written by Arpi Sharma; edited by Anand Kumar. *** Raytheon Assigned Patent ALEXANDRIA, Va., June 19 -- Raytheon, Waltham, Mass., has been assigned a patent (8,468,246) developed by James J. Mays, McKinney, Texas, Michael L. Williams, Rockwall, Texas, and Michael L. Forsman, Sachse, Texas, for a "system and method for allocating resources in a distributed computing system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "According to a particular embodiment of the present invention, a system and method for allocating resources in a distributed computing system are provided. In one embodiment, a distributed computing system includes a computing grid including a plurality of grid nodes, a web server configured in a service-oriented architecture and operable to provide one or more business applications to a plurality of clients by executing one or more services on the plurality of grid nodes, and a resource control system communicatively coupled to the web server. The resource control system is operable to receive one or more performance parameters of the business applications executed on the plurality of grid nodes, provision one or more of the grid nodes in response to the performance parameters falling below a predetermined minimum level, and un-provision one or more of the grid nodes in response to the performance parameters exceeding a predetermined maximum level. The plurality of clients comprises a plurality of client subsets, each client subset requiring a respective quality of service, and each of the grid nodes in the computing grid is assigned a particular client subset for which to execute services." The patent application was filed on April 13, 2009 (12/422,653). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,246&OS=8,468,246&RS=8,468,246 Written by Arpi Sharma; edited by Anand Kumar. *** International Business Machines Assigned Patent for Dynamic Memory Affinity Reallocation After Partition Migration ALEXANDRIA, Va., June 19 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,468,289) developed by David Alan Hepkin, Austin, Texas, Peter Joseph Heyrman, Rochester, Minn., and Bret Ronald Olszewski, Austin, Texas, for a "dynamic memory affinity reallocation after partition migration." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of dynamically reallocating memory affinity in a virtual machine after migrating the virtual machine from a source computer system to a destination computer system migrates processor states and resources used by the virtual machine from the source computer system to the destination computer system. The method maps memory of the virtual machine to processor nodes of the destination computer system. The method deletes memory mappings in processor hardware, such as translation lookaside buffers and effective-to-real address tables, for the virtual machine on the destination computer system. The method starts the virtual machine on the destination computer system in virtual real memory mode. A hypervisor running on the destination computer system receives a page fault and virtual address of a page for said virtual machine from a processor of the destination computer system and determines if the page is in local memory of the processor. If the hypervisor determines the page to be in the local memory of the processor, the hypervisor returning a physical address mapping for the page to the processor. If the hypervisor determines the page not to be in the local memory of the processor, the hypervisor moves the page to local memory of the processor and returns a physical address mapping for said page to the processor." The patent application was filed on Oct. 22, 2010 (12/910,234). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,468,289&OS=8,468,289&RS=8,468,289 Written by Arpi Sharma; edited by Anand Kumar. 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