[May 24, 2013] Actel Assigned Patent Tweet (Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service ALEXANDRIA, Va., May 24 -- Actel, San Jose, Calif., has been assigned a patent (8,446,170) developed by four co-inventors for an "FPGA RAM blocks optimized for use as register files." The co-inventors are Joel Landry, Colorado Springs, Colo., Jonathan Greene, Palo Alto, Calif., William C. Plants, Campbell, Calif., and Wenyi Feng, Sunnyvale, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described." The patent application was filed on May 3, 2012 (13/463,232). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,446,170.PN.&OS=PN/8,446,170&RS=PN/8,446,170 Written by Kusum Sangma; edited by Anand Kumar. KS0524AK0524-880691 (c) 2013 Targeted News Service [ Back To TMCnet.com's Homepage ]