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U.S. Patents Awarded to Inventors in Idaho (May 23)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., May 23 -- The following federal patents were awarded to inventors in Idaho. *** Micron Technology Assigned Patent for Digit Line Comparison Circuits ALEXANDRIA, Va., May 23 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,446,783) developed by Dean A. Klein, Eagle, Idaho, for "digit line comparison circuits." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier." The patent application was filed on Sept. 10, 2012 (13/608,634). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,46,783.PN.&OS=PN/84,46,783&RS=PN/84,46,783 Written by Amal Ahmed; edited by Jaya Anand. *** Micron Technology Assigned Patent for Memories and their Formation ALEXANDRIA, Va., May 23 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,446,767) developed by Sanh D. Tang, Boise, Idaho, and Nishant Sinha, Boise, Idaho, for "memories and their formation." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the first and second vertical levels, and a second data line over the first data line is selectively coupled to the second memory cells at the first and second vertical levels." The patent application was filed on July 2, 2010 (12/829,860). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,46,767.PN.&OS=PN/84,46,767&RS=PN/84,46,767 Written by Amal Ahmed; edited by Jaya Anand. *** Micron Technology Assigned Patent for Variable Resistance Memory Programming ALEXANDRIA, Va., May 23 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,446,758) developed by Xiaonan Chen, Boise, Idaho, for "variable resistance memory programming." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Some embodiments include a device having memory elements and methods of storing information into the memory elements. Such methods can include increasing a temperature of a portion of a memory element for a time interval during an operation to change a resistance state of the memory element. After the time interval, the methods can include decreasing the temperature of the portion of the memory element. Decreasing the temperature can be performed using a signal having a first negative slope and a second negative slope. Other embodiments are described." The patent application was filed on Dec. 14, 2010 (12/967,592). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,46,758.PN.&OS=PN/84,46,758&RS=PN/84,46,758 Written by Amal Ahmed; edited by Jaya Anand. *** Micron Technology Assigned Patent for Methods of Making a Semiconductor Memory Device ALEXANDRIA, Va., May 23 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,446,762) developed by Sanh D. Tang, Boise, Idaho, Gordon A. Haller, Boise, Idaho, and Daniel H. Doyle, Eagle, Idaho, for "methods of making a semiconductor memory device." The abstract of the patent published by the U.S. Patent and Trademark Office states: "One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic "1" is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held." The patent application was filed on March 25, 2011 (13/071,979). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,46,762.PN.&OS=PN/84,46,762&RS=PN/84,46,762 Written by Amal Ahmed; edited by Jaya Anand. *** Micron Technology Assigned Patent for Communication Methods, Methods of Forming an Interconnect, Signal Interconnects, Integrated Circuit Structures, Circuits, and Data Apparatuses ALEXANDRIA, Va., May 23 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,447,147) developed by Chandra Mouli, Boise, Idaho, for a "communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Some embodiments include communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses. In one embodiment, a communication method includes accessing an optical signal comprising photons to communicate information, accessing an electrical signal comprising electrical data carriers to communicate information, and using a single interconnect, communicating the optical and electrical signals between a first spatial location and a second spatial location spaced from the first spatial location." The patent application was filed on Dec. 12, 2011 (13/323,708). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,447,147.PN.&OS=PN/8,447,147&RS=PN/8,447,147 Written by Kusum Sangma; edited by Anand Kumar. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1125914 (c) 2013 Targeted News Service |