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U.S. Patents Awarded to Inventors in Oregon (May 17)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., May 17 -- The following federal patents were awarded to inventors in Oregon. *** STMicroelectronics Assigned Patent ALEXANDRIA, Va., May 17 -- STMicroelectronics, Coppell, Texas, has been assigned a patent (8,441,712) developed by Michele Palmieri, Corvallis, Ore., for a switchable display system. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A display system for a portable device is switchable by electrical addressing. The display system can absorb ambient light and reflect at least a portion of the absorbed light to render an image on a surface of the display. The display includes a plurality of pixel electrodes. Each of the plurality of pixel electrodes includes linkers with acceptor molecules and donor molecules that form groups having respective color properties. In an off-state, a respective pixel is configured to reflect white light. In an on-state, a respective pixel is configured to reflect light according to the molecular grouping of the acceptor-donor group." The patent application was filed on Oct. 15, 2010 (12/925,181). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,441,712&OS=8,441,712&RS=8,441,712 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Apple Assigned Patent for Light Sensitive Display with Object Detection Calibration ALEXANDRIA, Va., May 17 -- Apple, Cupertino, Calif., has been assigned a patent (8,441,422) developed by four co-inventors for a "light sensitive display with object detection calibration." The co-inventors are Adiel Abileah, Portland, Ore., Willem den Boer, Hillsboro, Ore., Richard T. Tuenge, Hillsboro, Ore., and Terrance S. Larsson, Sherwood, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system comprising a stack of layers configured to display an image and including multiple elements configured to sense light. The system is configured to obtain a first reference image based on output from the multiple elements in a dark lighting condition associated with the system, and calibrate object detection based on output from the multiple elements using the obtained reference image. Additionally, a system comprising a display having a stack of layers configured to display an image and including a first and second set of elements. Each of the elements in the first set is configured to sense light, and each of the elements in the second set is configured to sense a dark current. The system is configured to perform object detection based on output from the elements in the first set, and calibrate the object detection based on output from the elements in the second set." The patent application was filed on Sept. 24, 2009 (12/566,455). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,441,422&OS=8,441,422&RS=8,441,422 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Digimarc Assigned Patent ALEXANDRIA, Va., May 17 -- Digimarc, Beaverton, Ore., has been assigned a patent (8,442,264) developed by Geoffrey B. Rhoads, West Linn, Ore., Kenneth L. Levy, Stevenson, Wash., and Tyler J. McKinley, Lake Oswego, Ore., for a "control signals in streaming audio or video indicating a watermark." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatuses for searching for a control signal in streaming video or streaming audio that indicates the presence of a watermark in the streaming video or streaming audio. The streaming video or streaming audio is received and searched for a control signal. The detection of a control signal indicates the presences of a digital watermark in the streaming video or streaming audio. An indicator is triggered based upon detecting the control signal." The patent application was filed on April 19, 2011 (13/089,816). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,442,264&OS=8,442,264&RS=8,442,264 Written by Arpi Sharma; edited by Anand Kumar. *** Intel Assigned Patent for Method of Implementing One Way Hash Functions and Apparatus ALEXANDRIA, Va., May 17 -- Intel, Santa Clara, Calif., has been assigned a patent (8,442,217) developed by Shay Gueron, Haifa, Israel, and Michael Kounavis, Portland, Ore., for a "method of implementing one way hash functions and apparatus therefor." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A cryptographic system for encrypting a data stream to be transported over a network by using a one way hash function constructed according to Merkle-Damgard construction includes a plurality of Davies-Mayer structure modules. A Davies-Mayer module modifies two variables A and B according to at least four words by no more than three Advanced Encryption Standard (AES) block cipher rounds." The patent application was filed on Sept. 8, 2009 (12/555,033). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,442,217&OS=8,442,217&RS=8,442,217 Written by Arpi Sharma; edited by Anand Kumar. *** Intel Assigned Patent ALEXANDRIA, Va., May 17 -- Intel, Santa Clara, Calif., has been assigned a patent (8,441,241) developed by four co-inventors for "methods and systems to digitally balance currents of a multi-phase voltage regulator." The co-inventors are Harish K. Krishnamurthy, Hillsboro, Ore., Annabelle Pratt, Hillsboro, Ore., Gene Frederiksen, Hillsboro, Ore., and Krishnan Ravichandran, Saratoga, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and systems to generate a digital error indication of an input signal relative to a reference signal, using resistors, comparators, and latches. The digital error indication may indicate that the input signal is within a range of the reference signal, above the range, or below the range. The methods and systems may be implemented within a multi-phase digital voltage regulator to generate a digital error indication for each of a plurality of phase currents relative to an instantaneous average of the phase currents. The digital voltage regulator may be fabricated on an integrated circuit die with a corresponding load, such as a processor. The digital voltage regulator may include a plurality of multiplier or look-up based gain modules, each to receive a corresponding one of the digital error signals and to output one of three values. Outputs of each gain module may be integrated over time." The patent application was filed on May 3, 2010 (12/772,366). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,441,241.PN.&OS=PN/8,441,241&RS=PN/8,441,241 Written by Kusum Sangma; edited by Anand Kumar. *** Lattice Semiconductor Assigned Patent ALEXANDRIA, Va., May 17 -- Lattice Semiconductor, Hillsboro, Ore., has been assigned a patent (8,441,284) developed by Wei Han, Beaverton, Ore., Mose Wahlstrom, Aloha, Ore., and Warren Juenemann, Cornelius, Ore., for a "flexible updating of multi-bit registers." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Various techniques are provided to flexibly update data fields stored in multi-bit registers. In one example, a method of updating a control register within an integrated circuit includes storing a plurality of initial bit values in the control register within the integrated circuit. The method also includes receiving a data set comprising one or more corrective bit values and one or more non-corrective bit values. The method also includes performing a logic operation on the received data set and the initial bit values to provide updated bit values. The method also includes replacing the initial bit values with the updated bit values in the control register." The patent application was filed on June 7, 2011 (13/154,885). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,441,284.PN.&OS=PN/8,441,284&RS=PN/8,441,284 Written by Kusum Sangma; edited by Anand Kumar. *** Hospital for Special Surgery, Princeton University, Texas A&M University System Assigned Patent ALEXANDRIA, Va., May 17 -- Hospital for Special Surgery, New York, Princeton University, Princeton, N.J., and Texas A&M University System, College Station, Texas, have been assigned a patent (8,440,618) developed by five co-inventors for a "composition for the attachment of implants to collagen or other components of biological tissue." The co-inventors are Suzanne A. Maher, Highland Lakes, N.J., Jeffrey Schwartz, Princeton, N.J., Axel Oscar Magnus Hook, Houston, Brooke Hageman Russell, Pearland, Texas, and Casey Marie Jones, Portland, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention relates to a novel composition comprising an implant, scaffold or construct bound to a biological or chemical moiety. The bound moiety has the ability to bind to a component of the extracellular matrix of biological tissue, allowing the implant to be bound to the biological tissue in a short period of time after implantation. The invention also relates to the use and manufacture of this novel composition, as well as a novel use for the protein CNA." The patent application was filed on Jan. 19, 2012 (13/353,952). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,40,618.PN.&OS=PN/84,40,618&RS=PN/84,40,618 Written by Amal Ahmed; edited by Jaya Anand. *** Intel Assigned Patent for Substrate Fins with Different Heights ALEXANDRIA, Va., May 17 -- Intel, Santa Clara, Calif., has been assigned a patent (8,441,074) developed by Willy Rachmady, Beaverton, Ore., Justin S. Sandford, Tigard, Ore., and Michael K. Harper, Hillsboro, Ore., for a "substrate fins with different heights." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas." The patent application was filed on July 15, 2010 (12/837,321). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,441,074&OS=8,441,074&RS=8,441,074 Written by Arpi Sharma; edited by Anand Kumar. *** Intel Assigned Patent for Methods to Form Memory Devices having a Capacitor with a Recessed Electrode ALEXANDRIA, Va., May 17 -- Intel, Santa Clara, Calif., has been assigned a patent (8,441,097) developed by five co-inventors for "methods to form memory devices having a capacitor with a recessed electrode." The co-inventors are Joseph M. Steigerwald, Forest Grove, Ore., Nick Lindert, Beaverton, Ore., Steven J. Keating, Beaverton, Ore., Christopher J. Jezewski, Hillsboro, Ore., and Timothy E. Glassman, Portland, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods to form memory devices having a MIM capacitor with a recessed electrode are described. In one embodiment, a method of forming a MIM capacitor with a recessed electrode includes forming an excavated feature defined by a lower portion that forms a bottom and an upper portion that forms sidewalls of the excavated feature. The method includes depositing a lower electrode layer in the feature, depositing an electrically insulating layer on the lower electrode layer, and depositing an upper electrode layer on the electrically insulating layer to form the MIM capacitor. The method includes removing an upper portion of the MIM capacitor to expose an upper surface of the electrode layers and then selectively etching one of the electrode layers to recess one of the electrode layers. This recess isolates the electrodes from each other and reduces the likelihood of a current leakage path between the electrodes." The patent application was filed on Dec. 23, 2009 (12/646,957). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,441,097&OS=8,441,097&RS=8,441,097 Written by Arpi Sharma; edited by Anand Kumar. *** Intel Assigned Patent for Embedded Memory Device having MIM Capacitor Formed in Excavated Structure ALEXANDRIA, Va., May 17 -- Intel, Santa Clara, Calif., has been assigned a patent (8,441,057) developed by eight co-inventors for an "embedded memory device having MIM capacitor formed in excavated structure." The co-inventors are Steven J. Keating, Beaverton, Ore., Nick Lindert, Beaverton, Ore., Nadia Rahhal-Orabi, Hillsboro, Ore., Brian Doyle, Portland, Ore., Satyarth Suri, Hillsboro, Ore., Swaminathan Sivakumar, Beaverton, Ore., Lana Jong, Hillsboro, Ore., and Lin Sha, Portland, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device." The patent application was filed on Feb. 16, 2011 (13/028,400). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,441,057&OS=8,441,057&RS=8,441,057 Written by Arpi Sharma; edited by Anand Kumar. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1125265 (c) 2013 Targeted News Service |