[May 15, 2013] Altera Assigned Patent for Reassembling Scattered Logic Blocks in Integrated Circuits Tweet (Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service ALEXANDRIA, Va., May 15 -- Altera, San Jose, Calif., has been assigned a patent (8,443,327) developed by Mohd Mawardi Bin Mohd Razha, Bayan Lepas, Malaysia, and Jinyong Yuan, Cupertino, Calif., for "reassembling scattered logic blocks in integrated circuits." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques for reassembling scattered logic blocks in an integrated circuit (IC) are provided. The techniques include identifying a virtual memory block to be reassembled in an IC design. The virtual memory block is formed by a plurality of memory blocks that are connected by a plurality of logic circuitry. The plurality of memory blocks and the plurality logic circuitry that connect the memory blocks within the virtual memory block are identified. The identified logic circuitry and memory blocks are removed from the virtual memory block. The virtual memory block is replaced with a custom memory block that is functionally comparable to the plurality of connected memory blocks in the virtual memory block." The patent application was filed on Feb. 22, 2011 (13/031,801). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,443,327&OS=8,443,327&RS=8,443,327 Written by Satyaban Rath; edited by Hemanta Panigrahi. SR0515HP0515-877242 (c) 2013 Targeted News Service [ Back To TMCnet.com's Homepage ]