[May 15, 2013] Synopsys Assigned Patent for Transformation of IC Designs for Formal Verification Tweet (Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service ALEXANDRIA, Va., May 15 -- Synopsys, Mountain View, Calif., has been assigned a patent (8,443,317) developed by Muzaffer Hiraoglu, Chelmsford, Mass., and Peter Wilhelm Josef Zepter, Mountain View, Calif., for "transformation of IC designs for formal verification." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A non-transitory computer readable storage media, a computer-implemented method and apparatus for electronic design automation are disclosed. A reference integrated circuit (IC) design and a remitted IC design are received. Instances of cells of the reference IC design and the retimed IC designed are replaced with replacement circuits based on a description of moves of retiming associated with the reference IC design and the synthesized IC design. A comparison of the reference IC design and the retimed IC designed is performed to determine whether the retimed IC design is equivalent to the transformed IC design." The patent application was filed on July 29, 2009 (12/511,987). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,443,317&OS=8,443,317&RS=8,443,317 Written by Satyaban Rath; edited by Hemanta Panigrahi. SR0515HP0515-877248 (c) 2013 Targeted News Service [ Back To TMCnet.com's Homepage ]