[May 02, 2013] Rambus Assigned Patent for Multi-column Addressing Mode Memory System including an Integrated Circuit Memory Device Tweet (Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service ALEXANDRIA, Va., May 2 -- Rambus, Sunnyvale, Calif., has been assigned a patent (8,432,766) developed by four co-inventors for a "multi-column addressing mode memory system including an integrated circuit memory device." The co-inventors are Frederick A. Ware, Los Altos Hills, Calif., Lawrence Lai, San Jose, Calif., Chad A. Bellows, Burlingame, Calif., and Wayne S. Richardson, Saratoga, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface." The patent application was filed on March 1, 2012 (13/410,254). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=84,32,766.PN.&OS=PN/84,32,766&RS=PN/84,32,766 Written by Amal Ahmed; edited by Jaya Anand. AM0502JA0502-872850 (c) 2013 Targeted News Service [ Back To TMCnet.com's Homepage ]