[March 29, 2013] OCP-IP Launches OCP Debug Socket Specification 2.0 Tweet Mar 29, 2013 (Close-Up Media via COMTEX) -- Open Core Protocol International Partnership (OCP-IP) has released the OCP Debug Socket Specification 2.0. In a release on March 26, the Company noted that the latest version now includes support for Low Power Signaling as well as Cache Coherence signals that are available in the current version of the OCP specification. This allows the most complex processors to be debugged with exact visibility of traffic to or from the OCP bus on all levels of transactions, including all transfer states. The additional debug signal interface definitions provided by the OCP Debug Socket Specification 2.0 ensure OCP is a complete multicore SoC socket. It addresses the visibility and control needed to best analyze the operation of OCP architectures and their design flows and provides a common set of debug options with consistent signal interfaces. "With the evolution of heterogeneous Multi-Core Systems On the Chip (MC-SoC) the debug interconnection deserves special attention," said Ian Mackintosh, President of OCP-IP. "A set of standardized signaling and definitions make the debug wiring core-independent to match the OCP standard, and in doing so stimulates the development of predefined and verified debug IP blocks for quick and successful assembly of large MC-SoCs." Non-Members may access their copy by completing the Research License Agreement. OCP-IP is a non-profit corporation promoting, supporting and delivering an openly licensed, core-centric protocol fulfilling integration requirements of heterogeneous multicore systems. More information: www.OCPIP.org ((Comments on this story may be sent to [email protected])) [ Back To TMCnet.com's Homepage ]