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U.S. Patents Awarded to Inventors in Oregon (Jan. 4)
(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service
Targeted News Service
ALEXANDRIA, Va., Jan. 4 -- The following federal patents were awarded to inventors in Oregon.
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Unity Semiconductor Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- Unity Semiconductor, Sunnyvale, Calif., has been assigned a patent (8,344,756) developed by Robert Norman, Pendleton, Ore., for a "field programmable gate arrays using resistivity-sensitive memories."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane."
The patent application was filed on March 8, 2011 (12/932,902). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,344,756&OS=8,344,756&RS=8,344,756
Written by Arpi Sharma; edited by Anand Kumar.
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Intel Assigned Patent for Channel Access Mechanism for Wide Channels Used in Overlapping Networks
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,345,547) developed by Minyoung Park, Portland, Ore., for a "channel access mechanism for wide channels used in overlapping networks."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "When a device is contending for the right to transmit on a wide channel (composed of a primary narrow channel and one or more secondary narrow channels), it may halt its backoff counter if one of the secondary channels is detected as busy, and restart the backoff counter from its halted value when all the channels are again detected as idle. Some embodiments may use a guard interval detection technique to aid in sensing whether the secondary channels are busy."
The patent application was filed on Aug. 23, 2010 (12/861,086). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,345,547&OS=8,345,547&RS=8,345,547
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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WIMM Labs Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- WIMM Labs, Los Altos, Calif., has been assigned a patent (8,345,414) developed by five co-inventors for a wearable computing module. The co-inventors are David J. Mooring, Los Altos Hills, Calif., Mark A. Ross, San Carlos, Calif., Michael F. Gifford, San Jose, Calif., Troy J. Edwards, San Jose, Calif., and Jason A. Hilbourne, Portland, Ore.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "In an example embodiment, a computing module includes a case, an optical display subsystem coupled to the case, a circuit element assembly, a power cell and an interface connector. The case includes a bottom portion and multiple lateral sidewalls. The case defines an enclosure. The circuit element assembly is positioned within the enclosure and is coupled to the optical display subsystem. The power cell is coupled to the circuit element assembly. The interface connector is defined in the case and includes multiple side openings, multiple bottom openings and multiple connector pads. The side openings are defined in at least one of the lateral sidewalls. The bottom openings are defined in the bottom portion of the case. The connector pads include multiple side pads coupled to the case and in communication with the side openings and multiple bottom pads coupled to the case and in communication with the bottom openings."
The patent application was filed on Oct. 15, 2010 (12/905,888). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,345,414&OS=8,345,414&RS=8,345,414
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Digimarc Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- Digimarc, Beaverton, Ore., has been assigned a patent (8,345,316) developed by Brett A. Bradley, Portland, Ore., Brett T. Hannigan, Philadelphia, and John Kennedy Barr, Tigard, Ore., for a "layered security in digital watermarking."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A media object authentication system uses layers of security features based on digital watermarks embedded in media objects. The system generates a first digital watermark with a message payload carrying data about the object, such as a hash of text data printed on the object. The first digital watermark is combined with a content signature derived from features of the media object, such as frequency domain attributes, edge attributes, or other filtered version of the media signal (e.g., image photo on a secure document) on the media object. This combination forms a new digital watermark signal that is embedded in the host media object. To verify the object, the digital watermark payload is extracted and compared with the data about the object. The combined digital watermark and content signature is also evaluated to authenticate the media signal on the media object."
The patent application was filed on April 13, 2009 (12/422,715). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,345,316&OS=8,345,316&RS=8,345,316
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Intel Assigned Patent for Methods, Systems, and Data Structures for Generating a Rasterizer
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,345,059) developed by William A. Hux, Portland, Ore., and Stephen Junkins, Bend, Ore., for "methods, systems, and data structures for generating a rasterizer."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a shell rasterizer. The machine architecture is used for selecting replacement logic that replaces portions of shell logic in the shell rasterizer. The machine architecture is used for selectively inserting memory management logic into portions of the shell logic to produce."
The patent application was filed on July 11, 2012 (13/546,788). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,345,059&OS=8,345,059&RS=8,345,059
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Intel Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,344,425) developed by nine co-inventors for "multi-gate III-V quantum well structures." The co-inventors are Marko Radosavljevic, Beaverton, Ore., Uday Shah, Portland, Ore., Gilbert Dewey, Hillsboro, Ore., Niloy Mukherjee, Beaverton, Ore., Robert S. Chau, Beaverton, Ore., Jack Kavalieros, Portland, Ore., Ravi Pillarisetty, Portland, Ore., Titash Rakshit, Hillsboro, Ore., and Matthew V. Metz, Portland, Ore.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods of forming microelectronic structures are described. Embodiments of those methods include forming a III-V tri-gate fin on a substrate, forming a cladding material around the III-V tri-gate fin, and forming a hi k gate dielectric around the cladding material."
The patent application was filed on Dec. 30, 2009 (12/655,463). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,44,425.PN.&OS=PN/83,44,425&RS=PN/83,44,425
Written by Amal Ahmed; edited by Jaya Anand.
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AUTODESK Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- AUTODESK, San Rafael, Calif., has been assigned a patent (8,345,056) developed by four co-inventors for an "user-directed path-based region filling." The co-inventors are Michael Perani, San Rafael, Calif., Scott Morrison, Portland, Ore., Yan E. Schober, San Francisco, and Jian Zheng, Greenbrae, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for filling closed regions in a drawing using a region filling tool. Rather than selecting individual regions to fill, or filling based on style-by-layer techniques, the user creates a path or an area boundary to identify the regions to be filled. A graphics application may then fill each region that intersects the path or area boundary with a selected color or graphical style. In this manner, multiple regions in the drawing may be identified using one interaction with the region filling tool, allowing the user to more efficiently and intuitively fill regions in the drawing with the selected color or graphical style."
The patent application was filed on Jan. 18, 2008 (12/016,909). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,345,056&OS=8,345,056&RS=8,345,056
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Intel Assigned Patent for Materials for Interfacing High-K Dielectric Layers with III-V Semiconductors
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,344,418) developed by four co-inventors for "materials for interfacing high-K dielectric layers with III-V semiconductors." The co-inventors are Willy Rachmady, Beaverton, Ore., Marko Radosavljevic, Beaverton, Ore., Gilbert Dewey, Hillsboro, Ore., and Robert S. Chau, Beaverton, Ore.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A group III chalcogenide layer for interfacing a high-k dielectric to a III-V semiconductor surface and methods of forming the same. A III-V QWFET includes a gate stack which comprises a high-K gate dielectric layer disposed on an interfacial layer comprising a group III chalcogenide. In an embodiment, a III-V semiconductor surface comprising a native oxide is sequentially exposed to TMA and H.sub.2S provided in an ALD process to remove substantially all the native oxide and form an Al.sub.2S.sub.3 layer on the semiconductor surface."
The patent application was filed on Dec. 23, 2009 (12/646,436). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,44,418.PN.&OS=PN/83,44,418&RS=PN/83,44,418
Written by Amal Ahmed; edited by Jaya Anand.
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Intel Assigned Patent for Using Unstable Nitrides to form Semiconductor Structures
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,344,352) developed by five co-inventors for "using unstable nitrides to form semiconductor structures." The co-inventors are Juan E. Dominguez, Hillsboro, Ore., Adrien R. Lavoie, Beaverton, Ore., John J. Plombon, Portland, Ore., Joseph H. Han, San Jose, Calif., and Harsono S. Simka, Saratoga, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Incompatible materials, such as copper and nitrided barrier layers, may be adhered more effectively to one another. In one embodiment, a precursor of copper is deposited on the nitrided barrier. The precursor is then converted, through the application of energy, to copper which could not have been as effectively adhered to the barrier in the first place."
The patent application was filed on July 18, 2011 (13/185,094). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,44,352.PN.&OS=PN/83,44,352&RS=PN/83,44,352
Written by Amal Ahmed; edited by Jaya Anand.
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Neofocal Systems Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- Neofocal Systems, Portland, Ore., has been assigned a patent (8,344,659) developed by Tsutomu Shimomura, Incline Village, Nev., Mark Peting, Yamhill, Ore., and Dale Beyer, Portland, Ore., for a "system and method for lighting power and control system."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Light Emitting Diodes (LEDs) are increasingly used in illumination applications. To control multiple Light Emitting Diodes (LEDs), or any other controllable light source, this document introduces a single-wire multiple-LED power and control system. Specifically, individually controlled LED units are arranged in a series configuration that is driven by a control unit located at the head of the series. Each of the individually controlled LED units may comprise more than one LED that is also individually controllable. The head-end control unit provides both electrical power and control signals down a single wire to drive all of the LED units in the series in a manner that allows each LED unit to be controlled individually or in assigned groups."
The patent application was filed on Nov. 6, 2009 (12/590,449). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,344,659&OS=8,344,659&RS=8,344,659
Written by Arpi Sharma; edited by Anand Kumar.
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Advanced Energy Industries Assigned Patent for System and Method of Determining Maximum Power Point Tracking for a Solar Power Inverter
ALEXANDRIA, Va., Jan. 4 -- Advanced Energy Industries, Fort Collins, Colo., has been assigned a patent (8,344,547) developed by John M. Fife, Bend, Ore., Michael A. Mills-Price, Bend, Ore., and Steven G. Hummel, Bend, Ore., for a "system and method of determining maximum power point tracking for a solar power inverter."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for operating a photovoltaic element at or near a maximum power point. A maximum power point tracker changes a voltage or current set point of a photovoltaic element in sequential discrete steps, measuring an output power at each step after a predetermined settling time. A slope of a power-voltage curve is then estimated and the slope is corrected for irradiance changes. Finally, an operating voltage or current of the photovoltaic element is adjusted based on the slope of the power-voltage curve and other factors, causing the photovoltaic element to operate at or near its maximum power."
The patent application was filed on May 16, 2011 (13/108,135). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,344,547&OS=8,344,547&RS=8,344,547
Written by Arpi Sharma; edited by Anand Kumar.
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Maxim Integrated Products Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- Maxim Integrated Products, San Jose, Calif., has been assigned a patent (8,344,478) developed by four co-inventors for "inductors having inductor axis parallel to substrate surface." The co-inventors are Joseph P. Ellul, San Jose, Calif., Khanh Tran, Milpitas, Calif., Edward Martin Godshalk, Newberg, Ore., and Albert Bergemont, Palo Alto, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed."
The patent application was filed on Oct. 23, 2009 (12/605,010). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,344,478&OS=8,344,478&RS=8,344,478
Written by Arpi Sharma; edited by Anand Kumar.
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Intel Assigned Patent for Metal Gate Transistors with Raised Source and Drain Regions Formed on Heavily Doped Substrate
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,344,452) developed by Nick Lindert, Beaverton, Ore., Justin K. Brask, Portland, Ore., and Andrew Westmeyer, Beaverton, Ore., for a "metal gate transistors with raised source and drain regions formed on heavily doped substrate."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor."
The patent application was filed on Jan. 24, 2008 (12/011,439). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,344,452&OS=8,344,452&RS=8,344,452
Written by Arpi Sharma; edited by Anand Kumar.
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Radar Engineers Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- Radar Engineers, Portland, Ore., has been assigned a patent (8,346,405) developed by Bartley Arthur Johnson, Portland, Ore., and Forrest S. Seitz, Beaverton, Ore., for a "map interface for electrical system discharge trace playback."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A diagnostic instrument for sources of electrical system discharges provides a map interface for controlling playback of collected signal traces. A map pane of the interface displays a map of an area illustrating a path along which signal data was collected. A double click input selecting a location on the path causes playback of a waveform for the recorded signal in a signal pane commencing from the selected location."
The patent application was filed on Nov. 3, 2009 (12/611,857). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,346,405.PN.&OS=PN/8,346,405&RS=PN/8,346,405
Written by Kusum Sangma; edited by Anand Kumar.
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Intel Assigned Patent for Uplink Power Control for Wireless Systems
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,346,290) developed by Ali Taha Koc, Hillsboro, Ore., Shilpa Talwar, Santa Clara, Calif., and Changho Suh, Albany, Calif., for an "uplink power control for wireless systems."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques are described that can be used to determine a transmitter power level of a mobile station at cell edge. To determine transmitter power level, the technique considers at least a balance of power transmitted by mobile stations near cell edge and power transmitted by mobile stations closer to cell center, target mean received power by the base station from mobile stations near center cell, target mean power transmitted from cell edge mobile stations, signal-to-interference-power ratio between signals transmitted from base stations of different cells to the mobile station at cell edge, and channel gain."
The patent application was filed on Feb. 13, 2009 (12/378,382). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,346,290.PN.&OS=PN/8,346,290&RS=PN/8,346,290
Written by Kusum Sangma; edited by Anand Kumar.
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Intel Assigned Patent
ALEXANDRIA, Va., Jan. 4 -- Intel, Santa Clara, Calif., has been assigned a patent (8,346,305) developed by six co-inventors for a "theft deterrent techniques and secure mobile platform subscription for wirelessly enabled mobile devices." The co-inventors are Duncan Glendinning, Chandler, Ariz., Mojtaba Mirashrafi, Portland, Ore., Saurabh Dadu, Tigard, Ore., Mousumi M. Hazra, Beaverton, Ore., Gyan Prakash, Beaverton, Ore., and Carol A. Bell, Beaverton, Ore.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Theft deterrence and secure mobile platform subscription techniques for wireless mobile devices are described. An apparatus may comprise a removable secure execution module arranged to connect with a computing platform for a wireless mobile device. The removable secure execution module may comprise a first processing system to execute a security control module. The security control module may be operative to communicate with a security server over a wireless channel on a periodic basis to obtain a security status for the wireless mobile device. The security control module may output control directives to control operations for one or more components of the computing platform based on the security status. Other embodiments are described and claimed."
The patent application was filed on Sept. 25, 2009 (12/567,652). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,346,305.PN.&OS=PN/8,346,305&RS=PN/8,346,305
Written by Kusum Sangma; edited by Anand Kumar.
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