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MonolithIC 3D Assigned Patent
[October 29, 2012]

MonolithIC 3D Assigned Patent

(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service ALEXANDRIA, Va., Oct. 29 -- MonolithIC 3D, San Jose, Calif., has been assigned a patent (8,294,159) developed by five co-inventors for a "method for fabrication of a semiconductor device and structure." The co-inventors are Zvi Or-Bach, San Jose, Calif., Deepak C. Sekar, San Jose, Calif., Brian Cronquist, San Jose, Calif., Israel Beinglass, Sunnyvale, Calif., and Jan Lodewijk de Jong, Cupertino, Calif.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors." The patent application was filed on March 28, 2011 (13/073,268). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,294,159&OS=8,294,159&RS=8,294,159 Written by Arpi Sharma; edited by Anand Kumar.

AS1029AK1029-801249 (c) 2012 Targeted News Service

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