Freescale Semiconductor Assigned Patent for Data Processor Coupled to a Sequencer Circuit That Provides Efficient Scalable Queuing and Method
(Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service
ALEXANDRIA, Va., April 11 -- Freescale Semiconductor, Austin, Texas, has been assigned a patent (8,156,265) developed by Tim J. Buick, Ottawa, and John F. Pillar, Ottawa, for a "data processor coupled to a sequencer circuit that provides efficient scalable queuing and method."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A data processor includes a single-token-record memory, a sequence circuit, and a memory controller. The single-token-record memory has a plurality of first storage locations. The sequencer circuit is coupled to the single-token-record memory. The sequencer circuit, responsive to a request to place a token in a tail-end of a queue, either stores said token into one of the plurality of first storage locations if the single-token-record memory stores no greater than a predetermined number of tokens associated with the tail-end of the queue, or stores the token with at least one additional token and a pointer to a next storage location into one of a plurality of second storage locations otherwise. The memory controller is coupled to the sequencer circuit to store the token with the at least one additional token and the pointer in a location of a multi-token-record memory having the plurality of second storage locations."
The patent application was filed on June 2, 2009 (12/476,586). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,156,265&OS=8,156,265&RS=8,156,265
Written by Kusum Sangma; edited by Anand Kumar.
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