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U.S. Patents Awarded to Inventors in Oregon (Sept. 28)
[September 28, 2011]

U.S. Patents Awarded to Inventors in Oregon (Sept. 28)


(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Sept. 28 -- The following federal patents were awarded to inventors in Oregon.

*** Intel Assigned Patent ALEXANDRIA, Va., Sept. 28 -- Intel, Santa Clara, Calif., has been assigned a patent (8,028,341) developed by Antonio S. Cheng, Portland, Ore., and Francis X. McKeen, Portland, Ore., for a "providing extended memory protection." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, the present invention provides for extended memory protection for memory of a system. The embodiment includes a method for associating a protection indicator of a protection record maintained outside of an application's data space with a memory location, and preventing access to the memory location based on the status of the protection indicator. In such manner, more secure operation is provided, as malicious code or other malware is prevented from accessing protected memory locations. Other embodiments are described and claimed." The patent application was filed on Oct. 27, 2009 (12/606,408). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,028,341&OS=8,028,341&RS=8,028,341 Written by Satyaban Rath; edited by Hemanta Panigrahi.



*** Lyco Manufacturing Assigned Patent ALEXANDRIA, Va., Sept. 28 -- Lyco Manufacturing, Columbus, Wis., has been assigned a patent (RE42,732) developed by David R. Zittel, Columbus, Wis., Steven W. Hughes, Beaver Dam, Wis., and Daniel D. Maupin, Corvallis, Ore., for a "rotary blancher for processing food product." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and rotary blancher for processing food product using a heat transfer medium and directed flows of a fluid that can comprise a liquid, a gas, a vapor or a combination thereof. The directed flows can be discharged from orifices or banks of orifices that are distributed around the food products in the blancher. The flows are discharged at a high flow rate, a high pressure, or a combination of both. Where a liquid is discharged, it preferably is discharged at a flow rate of at least 20 gpm and at least 30 psi. Where a gas is discharged, it is discharged at a flow rate of at least 60 CFM at a pressure of at least 2 psi or at a flow rate of at least 10 CFM at a pressure of at least 80 psi. If desired, discharged fluid can be recirculated to save energy. To help increase agitation and help break up clumps of food products in the blancher, direct-contact mechanical agitation devices, such as baffles, can be used. Such a blancher and method can be used to process food product by blanching, cooking and pasteurizing, is suited for processing relatively heavy food products having a density of at least 55 lbs/ft.sup.3 using discharged liquid and gas, and is suited for processing food products having a lesser density using only discharged gas." The patent application was filed on March 2, 2004 (10/791,695). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=RE42,732&OS=RE42,732&RS=RE42,732 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Intel Assigned Patent for Apparatus, System, and Method for Persistent User-level Thread ALEXANDRIA, Va., Sept. 28 -- Intel, Santa Clara, Calif., has been assigned a patent (8,028,295) developed by 12 co-inventors for an "apparatus, system, and method for persistent user-level thread." The co-inventors are Gautham Chinya, Hillsboro, Ore., Hong Wang, Santa Clara, Calif., Prashant Sethi, Folsom, Calif., Shivnandan Kaushik, Portland, Ore., Bryant Bigbee, Scottsdale, Ariz., John Shen, San Jose, Calif., Richard Hankins, San Jose, Calif., Xiang Zou, Portland, Ore., Baiju V. Patel, Portland, Ore., Jason W. Brandt, Austin, Texas, Anil Aggarwal, Portland, Ore., and John L. Reid, Portland, Ore.


The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof." The patent application was filed on Sept. 30, 2005 (11/239,475). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,028,295&OS=8,028,295&RS=8,028,295 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Intel Assigned Patent ALEXANDRIA, Va., Sept. 28 -- Intel, Santa Clara, Calif., has been assigned a patent (8,028,131) developed by Krishnakanth Sistla, Hillsboro, Ore., for a "system and method for aggregating core-cache clusters in order to produce multi-core processors." The abstract of the patent published by the U.S. Patent and Trademark Office states: "According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a scalability agent unit that operates as an interface between an on-die interconnect and both multiple processor cores and memory." The patent application was filed on Nov. 29, 2006 (11/605,636). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,028,131.PN.&OS=PN/8,028,131&RS=PN/8,028,131 Written by Arpi Sharma; edited by Jaya Anand.

*** International Business Machines Assigned Patent for Virtual KVM Functionality for Computer Systems ALEXANDRIA, Va., Sept. 28 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,028,108) developed by four co-inventors for a "virtual KVM functionality for computer systems." The co-inventors are Arun Batish, Portland, Ore., Phong Doan Ly, Beaverton, Ore., Jason Charles Myers, Hillsboro, Ore., and Paul Vu, Tigard, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method, system, and computer program product for implementing virtual keyboard video mouse (KVM) switching functionality using a processing device in communication with a memory device is provided. Keyboard, video, and mouse signals for a first computer are redirected to be carried over a standardized serial bus connecting the first computer to a second computer. Each of the keyboard, video, and mouse signals are carried at predetermined frequencies. The keyboard, video, and mouse signals on the second computer are identified and separated. The keyboard, video, and mouse signals are passed to an operating system on the second computer. The keyboard, video, and mouse signals are used by the operating system to manage the first computer." The patent application was filed on March 10, 2009 (12/400,944). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,028,108.PN.&OS=PN/8,028,108&RS=PN/8,028,108 Written by Arpi Sharma; edited by Jaya Anand.

*** News Technologies Assigned Patent ALEXANDRIA, Va., Sept. 28 -- News Technologies, Portland, Ore., has been assigned a patent (8,027,893) developed by Steven A. Burrows, Lake Oswego, Ore., and John P. Elliott, Wilsonville, Ore., for "news induced automated electronic securities transactions." The abstract of the patent published by the U.S. Patent and Trademark Office states: "News information is received. It is determined if the news information contains a reference to a company. It is further determined if the news information matches criteria associated with the company. Securities are automatically trade upon determining that said news information contains a reference to the company and determining that said news information matches criteria associated with the company." The patent application was filed on Dec. 16, 2002 (10/321,124). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,027,893.PN.&OS=PN/8,027,893&RS=PN/8,027,893 Written by Shabnam Sheikh; edited by Jaya Anand.

*** Invention Science Fund I Assigned Patent ALEXANDRIA, Va., Sept. 28 -- Invention Science Fund I, Bellevue, Wash., has been assigned a patent (8,028,152) developed by Andrew Forsyth Glew, Hillsboro, Ore., for a "hierarchical multi-threading processor for executing virtual threads in a time-multiplexed fashion." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instruction pipeline elements. Each execution cluster includes a plurality of second-level instruction pipeline elements, where each of the second-level instruction pipeline elements corresponds with a respective first-level instruction pipeline element, and one or more instruction execution units operatively coupled with each of the second-level instruction pipeline elements, where the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements and the plurality of execution clusters." The patent application was filed on Oct. 31, 2007 (11/932,874). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8028152.PN.&OS=PN/8028152&RS=PN/8028152 Written by Kusum Sangma; edited by Anand Kumar.

*** University of Oregon Assigned Patent ALEXANDRIA, Va., Sept. 28 -- The University of Oregon, Eugene, Ore., has been assigned a patent (8,028,159) developed by Jun Li, Eugene, Ore., for a "security protocols for hybrid peer-to-peer file sharing networks." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In a hybrid peer-to-peer file sharing network including a receiver peer and a provider peer, the receiver sends the provider a ticket [710] obtained from a server authorizing the receiver to obtain a data object O. The receiver obtains a root value of a hash tree for the object, verifies its digital signature, and sends the provider peer a request for a block of data object O and a request for a corresponding set of hash values from the hash tree [714]. The receiver receives from the provider peer the block of O and the corresponding set of hash values of the hash tree [716] that do not contain any hash value in the local hash tree. The receiver sends the provider an acknowledgement of receipt [718], obtains a block key from the provider [720], decrypts the block, verifies the integrity of the block using the subset of hash values and the local hash tree for O, and updates the local hash tree by adding the subset of hash values to the local hash tree, as well as any newly calculated hash values [722]. The provider may submit to a server the acknowledgements as proof of its service to the receiver." The patent application was filed on Aug. 19, 2008 (12/229,135). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8028159.PN.&OS=PN/8028159&RS=PN/8028159 Written by Kusum Sangma; edited by Anand Kumar.

*** Synopsys Assigned Patent ALEXANDRIA, Va., Sept. 28 -- Synopsys, Mountain View, Calif., has been assigned a patent (8,028,253) developed by Martin Drapeau, Montreal, and Jeffrey P. Mayhew, Portland, Ore., for a "method and apparatus for determining mask layouts for a multiple patterning process." The abstract of the patent published by the U.S. Patent and Trademark Office states: "One embodiment provides a method for determining mask layouts.During operation, the system can receive a design intent. Next, the system can determine a set of critical edges in the design layout, and select a first edge and a second edge. The system can then determine a first trench and a second trench using the first edge and the second edge, respectively. Note that an edge of the first trench may substantially overlap with the first edge, and an edge of the second trench may substantially overlap with the second edge. Next, the system may assign the first trench and the second trench to the first mask layout and the second mask layout, respectively. The system can then increase the first trench and the second trench, thereby improving pattern fidelity. The resulting mask layouts may be used in a double patterning process Abstract." The patent application was filed on April 2, 2007 (11/732,268). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,028,253.PN.&OS=PN/8,028,253&RS=PN/8,028,253 Written by Kusum Sangma; edited by Anand Kumar.

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