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U.S. Patents Awarded to Inventors in Minnesota (Aug. 31)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Aug. 31 -- The following federal patents were awarded to inventors in Minnesota. *** Digital Intelligence Assigned Patent ALEXANDRIA, Va., Aug. 31 -- Digital Intelligence, Apple Valley, Minn., has been assigned a patent (8,010,347) developed by Carlos A. Ricci, Apple Valley, Minn., and Vladimir V. Kovtun, Inver Grove Heights, Minn., for a "signal decomposition, analysis and reconstruction apparatus and method." The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention provides a system and method for representing quasi-periodic ("qp") waveforms comprising, representing a plurality of limited decompositions of the qp waveform, wherein each decomposition includes a first and second amplitude value and at least one time value. In some embodiments, each of the decompositions is phase adjusted such that the arithmetic sum of the plurality of limited decompositions reconstructs the qp waveform. These decompositions are stored into a data structure having a plurality of attributes. Optionally, these attributes are used to reconstruct the qp waveform, or patterns or features of the qp wave can be determined by using various pattern-recognition techniques. Some embodiments provide a system that uses software, embedded hardware or firmware to carry out the above-described method. Some embodiments use a computer-readable medium to store the data structure and/or instructions to execute the method." The patent application was filed on April 15, 2010 (12/760,554). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,10,347.PN.&OS=PN/80,10,347&RS=PN/80,10,347 Written by Ruby Maibam; edited by Jaya Anand. *** International Business Machines Assigned Patent for using Profiling When a Shared Document is Changed in a Content Management System ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,896) developed by John Edward Petri, Lewiston, Minn., for a "using profiling when a shared document is changed in a content management system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A content management system (CMS) includes a content modification mechanism that detects a change to a shared document in the repository, and in response to the detected change, inserts applicability metadata in the shared document. The content modification mechanism may broadcast the change to each parent document. Each parent document votes on whether or not to accept the change. If enough of the parent documents accept the change (i.e. the votes meet a defined voting threshold), the applicability metadata is removed from the shared content. If not enough of the parent documents accept the change, the applicability metadata remains in the shared content, and a profile corresponding to the applicability metadata is created for each parent document that accepted the change. In this manner, profiling may be used to account for changes to shared content in a content management system." The patent application was filed on Sept. 13, 2007 (11/854,660). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=558&f=G&l=50&d=PTXT&s1=20110830.PD.&p=12&OS=ISD/08/30/2011&RS=ISD/08/30/2011 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Micron Technology Assigned Patent ALEXANDRIA, Va., Aug. 31 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,010,866) developed by Paul A. LaBerge, Shoreview, Minn., Joseph M. Jeddeloh, Shoreview, Minn., and James B. Johnson, Boise, Idaho, for a "memory system and method using stacked memory device dice, and system using the memory system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time." The patent application was filed on Dec. 6, 2010 (12/961,291). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=588&f=G&l=50&d=PTXT&s1=20110830.PD.&p=12&OS=ISD/08/30/2011&RS=ISD/08/30/2011 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Database Breakpoint Apparatus and Method ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,949) developed by six co-inventors for a "database breakpoint apparatus and method." The co-inventors are Eric Lawrence Barsness, Pine Island, Minn., Michael Brian Brutman, Rochester, Minn., Richard Dean Dettinger, Rochester, Minn., Mahdad Majd, Rochester, Minn., Brian Edward Olson, Rochester, Minn., and John Matthew Santosuosso, Rochester, Minn. The abstract of the patent published by the U.S. Patent and Trademark Office states: "An apparatus and method define the concept of a "database breakpoint." One or more conditions in the database are specified as a database breakpoint in a debug environment for debugging a computer program that accesses the database. When the database conditions exist, one or more debug functions may be performed with respect to the execution of the computer program. Examples of debug functions include halting execution of the computer program and halting operations to the database by other programs. With both the computer program and database halted, the user may then interrogate the database to determine its state, and may interrogate the program to determine its state. Database breakpoints greatly enhance the utility of a debugger by providing additional conditions for debugging a computer program that accesses a database." The patent application was filed on Dec. 15, 2007 (11/957,426). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,949&OS=8,010,949&RS=8,010,949 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Error Correcting Code with Chip Kill Capability and Power Saving Enhancement ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,875) developed by eight co-inventors for an "error correcting code with chip kill capability and power saving enhancement." The co-inventors are Alan G. Gara, Mount Kisco, N.Y., Dong Chen, Croton On Husdon, N.Y., Paul W. Coteus, Yorktown Heights, N.Y., William T. Flynn, Rochester, Minn., James A. Marcella, Rochester, Minn., Todd Takken, Brewster, N.Y., Barry M. Trager, Yorktown Heights, N.Y., and Shmuel Winograd, Scarsdale, N.Y. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data." The patent application was filed on June 26, 2007 (11/768,559). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&u=%2Fnetahtml%2FPTO%2Fsearch-adv.htm&r=579&f=G&l=50&d=PTXT&s1=20110830.PD.&p=12&OS=ISD/08/30/2011&RS=ISD/08/30/2011 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Enforcing Constraints from a Parent Table to a Child Table ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,568) developed by Mark Gregory Megerian, Rochester, Minn., for "enforcing constraints from a parent table to a child table." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An apparatus, system, and storage medium that, in an embodiment, receive a constraint command that specifies a parent table, a primary key in the parent table, a child table, and a foreign key in the child table, and enforce that all values for the primary key in the parent table are present in the foreign key in the child table. In an embodiment, the enforcing may include receiving an insert command that specifies a target key, a target value for the target key, and a target table; determining whether the target table matches the parent table and whether, within a transaction that includes the insert command, the child table includes at least one row with a foreign key value that equals the target value of the primary key; inserting the target value in the target table if the determining is true; and returning an error otherwise." The patent application was filed on July 21, 2008 (12/220,164). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,10,568&OS=80,10,568&RS=80,10,568 Written by Rajat Puri; edited by Jaya Anand. *** International Business Machines Assigned Patent ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,561) developed by Richard D. Dettinger, Rochester, Minn., Judy I. Djugash, New Brighton, Minn., and Daniel P. Kolz, Rochester, Minn., for "techniques for sharing persistently stored query results between multiple users." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and article of manufacture for managing access to query results and, more particularly, for managing access by multiple users to persistently stored query results, whereby at least some of the users may have different access rights. One embodiment provides a computer-readable storage medium for managing access to a query result obtained upon execution of a query against one or more databases. The computer-readable storage medium comprises creating security information configured for restricting access to the query result. The security information is associated with the query result. Access to some or all of the query result is granted to a requesting entity on the basis of the security information and an attribute of the requesting entity." The patent application was filed on July 17, 2008 (12/175,309). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,10,561&OS=80,10,561&RS=80,10,561 Written by Rajat Puri; edited by Jaya Anand. *** Silicon Graphics International Assigned Patent ALEXANDRIA, Va., Aug. 31 -- Silicon Graphics International, Fremont, Calif., has been assigned a patent (8,010,558) developed by Geoffrey Wehrman, Minneapolis, and Dean Roehrich, Eagan, Minn., for a "relocation of metadata server with outstanding DMAPI requests." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A cluster of computer system nodes share direct read/write access to storage devices via a storage area network using a cluster filesystem and operating system implementing DMAPI. Threads executing on a metadata client know when a DMAPI event is required, and generate the DMAPI event on their own initiative when necessary. A metadata server maintains DMAPI queues. If the metadata server relocates to another host, the DMAPI events in the DMAPI queues are moved transparently to users." The patent application was filed on July 17, 2003 (10/620,387). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,10,558&OS=80,10,558&RS=80,10,558 Written by Rajat Puri; edited by Jaya Anand. *** International Business Machines Assigned Patent for Network on Chip that Maintains Cache Coherency with Invalidate Commands ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,750) developed by four co-inventors for a "network on chip that maintains cache coherency with invalidate commands." The co-inventors are Miguel Comparan, Rochester, Minn., Russell D. Hoover, Rochester, Minn., Jamie R. Kuesel, Rochester, Minn., and Eric O. Mejdrich, Rochester, Minn. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A network on chip (`NOC`) including integrated processor (`IP`) blocks, routers, memory communications controllers, and network interface controller, wherein the memory communications controller configured to execute a memory access instruction and configured to determine a state of a cache line addressed by the memory access instruction, the state of the cache line being one of shared, exclusive, or invalid; the memory communications controller configured to broadcast an invalidate command to a plurality of IP blocks of the NOC if the state of the cache line is shared; and the memory communications controller configured to transmit an invalidate command only to an IP block that controls a cache where the cache line is stored if the state of the cache line is exclusive." The patent application was filed on Jan. 17, 2008 (12/015,975). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,750.PN.&OS=PN/8,010,750&RS=PN/8,010,750 Written by Arpi Sharma; edited by Jaya Anand. *** International Business Machines Assigned Patent for Direct Memory Access in a Hybrid Computing Environment ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,718) developed by four co-inventors for a "direct memory access in a hybrid computing environment." The co-inventors are Charles J. Archer, Rochester, Minn., James E. Carey, Rochester, Minn., Jeffrey M. Ceason, Holmen, Wis., and Philip J. Sanders, Rochester, Minn. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Direct memory access (`DMA`) in a hybrid computing environment that includes a host computer, an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where DMA includes identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol; segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments; pinning, by the system level message passing module, the memory segments against paging; and asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator." The patent application was filed on Feb. 3, 2009 (12/364,590). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,718.PN.&OS=PN/8,010,718&RS=PN/8,010,718 Written by Arpi Sharma; edited by Jaya Anand. *** International Business Machines Assigned Patent for Early Coherency Indication for Return Data in Shared Memory Architecture ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,682) developed by four co-inventors for an "early coherency indication for return data in shared memory architecture." The co-inventors are Wayne Melvin Barrett, Rochester, Minn., David Alan Shedivy, Rochester, Minn., Kenneth Michael Valk, Rochester, Minn., and Brian T. Vanderpool, Byron, Minn. The abstract of the patent published by the U.S. Patent and Trademark Office states: "In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced." The patent application was filed on Dec. 28, 2004 (11/023,706). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,682.PN.&OS=PN/8,010,682&RS=PN/8,010,682 Written by Arpi Sharma; edited by Jaya Anand. *** Sony Computer Entertainment, International Business Machines Assigned Patent ALEXANDRIA, Va., Aug. 31 -- Sony Computer Entertainment, Tokyo, and International Business Machines, Armonk, N.Y., have been assigned a patent (8,010,716) developed by four co-inventors for "methods and apparatus for supporting multiple configurations in a multi-processor system." The co-inventors are Takeshi Yamazaki, Kanagawa, Japan, Scott Douglas Clark, Rochester, Minn., Charles Ray Johns, Austin, Texas, and James Allan Kahle, Austin, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface." The patent application was filed on Aug. 18, 2010 (12/858,915). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,716.PN.&OS=PN/8,010,716&RS=PN/8,010,716 Written by Arpi Sharma; edited by Jaya Anand. *** International Business Machines Assigned Patent for Hardware Recovery Responsive to Concurrent Maintenance ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,838) developed by five co-inventors for a "hardware recovery responsive to concurrent maintenance." The co-inventors are Sheldon Ray Bailey, Rochester, Minn., Bradley W. Bishop, Rochester, Minn., Alongkorn Kitamorn, Austin, Texas, Erlander Lo, Austin, Texas, and Allegra R. Segura, Austin, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Disclosed is a computer implemented method, data processing system, and apparatus to respond to detection of a hardware interface error on a system bus, for example, during a concurrent maintenance operation. The service processor may receive an error on the system bus. The error identifies at least one field replaceable unit and may inhibit the suppression of clock signal to the field replaceable unit. The service processor adds an identifier of the field replaceable unit to an eligible Field Replaceable Unit (FRU) list. The service processor recursively adds at least one field replaceable unit that the field replaceable unit depends upon. The service processor suppresses the clock signal to the field replaceable unit. The service processor inhibits tagging the field replaceable unit as unusable for next initial program load." The patent application was filed on Nov. 20, 2008 (12/274,434). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,838.PN.&OS=PN/8,010,838&RS=PN/8,010,838 Written by Kusum Sangma; edited by Anand Kumar. *** Honeywell International Assigned Patent ALEXANDRIA, Va., Aug. 31 -- Honeywell International, Morristown, N.J., has been assigned a patent (8,010,846) developed by five co-inventors for a "scalable self-checking processing platform including processors executing both coupled and uncoupled applications within a frame." The co-inventors are Byron Birkedahl, Glendale, Ariz., Nicholas Wilt, Glendale, Ariz., Art McCready, Glendale, Ariz., Brendan Hall, Eden Prairie, Minn., and Aaron Larson, Shoreview, Minn. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and systems for a scalable self-checking processing platform are described herein. According to one embodiment, during an execution frame, a first processing element executes both a high-criticality application and a first low-criticality application. During that same execution frame, a second processing element executes both the high-criticality application and a second low-criticality application. The high-criticality application output from the first processing element is compared with that from the second processing element before the next execution frame, and a fault occurs when the output does not match. The low-criticality application is not duplicated or compared. This and other embodiments allow high-criticality applications to be appropriated checked while avoiding the over-dedication of resources to low-criticality applications that do not warrant self-checking." The patent application was filed on April 6, 2009 (12/419,153). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,846.PN.&OS=PN/8,010,846&RS=PN/8,010,846 Written by Kusum Sangma; edited by Anand Kumar. *** International Business Machines Assigned Patent for Hypervisor-enforced Isolation of Entities within a Single Logical Partition's Virtual Address Space ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,763) developed by five co-inventors for a "hypervisor-enforced isolation of entities within a single logical partition's virtual address space." The co-inventors are William J. Armstrong, Rochester, Minn., Orran Y. Krieger, Newton, Mass., Cathy May, Millwood, N.Y., Michal Ostrowski, Austin, Texas, and Randal C. Swanberg, Round Rock, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Access control to shared virtual address space within a single logical partition is provided. The access control includes: associating, by a hypervisor of the data processing system, a memory protection key with a portion of a single logical partition's virtual address space being shared by multiple entities, the key preventing access by one of the multiple entities to that portion of the virtual address space, and allowing access by another of the entities to that portion of the virtual address space; and locking by the hypervisor the memory protection key from modification by the one entity, wherein the locking prevents the one entity from modifying the key and thereby gaining access to the portion of the single logical partition's virtual address space with the associated memory protection key. In one embodiment, the one entity is the single logical partition itself, and the another entity is a partition adjunct." The patent application was filed on April 28, 2008 (12/111,041). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8010763.PN.&OS=PN/8010763&RS=PN/8010763 Written by Kusum Sangma; edited by Anand Kumar. *** International Business Machines Assigned Patent for Database Staging Area Read-through or Forced Flush with Dirty Notification ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,499) developed by Richard D. Dettinger, Rochester, Minn., Daniel P. Kolz, Rochester, Minn., and Richard J. Stevens, Rochester, Minn., for a "database staging area read-through or forced flush with dirty notification." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the present invention allow the results of a query to an operational datastore to be augmented with relevant data that may be stored in a staging area datastore. Upon receiving a query to the operational datastore, it is determined whether data relevant to the query is present in the staging area datastore. If relevant data is present, such data may be transformed, transferred and combined with data in the operational datastore. The query is then run against the combined data and the results displayed to the user." The patent application was filed on Dec. 23, 2008 (12/343,340). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,499.PN.&OS=PN/8,010,499&RS=PN/8,010,499 Written by Anjali Jha; edited by Jaya Anand. *** International Business Machines Assigned Patent for Method for Multicontext XML Fragment Reuse and Validation in a Content Management System ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,518) developed by John Edward Petri, Lewiston, Minn., for a "method for multicontext XML fragment reuse and validation in a content management system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Method, article and apparatus for the reusability of data objects such as XML document fragments managed by a content management system (CMS). Embodiments of the invention may be used to enforce validation requirements for a multi-context XML fragment (i.e., for a fragment referenced in two or more documents managed by the CMS). When changes are made to a multi-context fragment, the CMS may detect any validation problems and take corrective action to resolve the validation problem." The patent application was filed on Feb. 15, 2007 (11/675,239). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,518.PN.&OS=PN/8,010,518&RS=PN/8,010,518 Written by Anjali Jha; edited by Jaya Anand. *** International Business Machines Assigned Patent for Increasing Application Availability during Automated Enterprise Deployments ALEXANDRIA, Va., Aug. 31 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,010,504) developed by five co-inventors for an "increasing application availability during automated enterprise deployments." The co-inventors are Rohith Kottamangalam Ashok, Apex, N.C., Charles James Redlin, Rochester, Minn., Barry Charles Searle, Mississauga, Canada, Christopher Paul Vignola, Port Jervis, N.Y., and Leigh Allen Williamson, Austin, Texas. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of deploying enterprise applications or updates to data processing systems in a complex data processing environment. The enterprise applications or updates are phase deployed to the target data processing systems. Phased deployment includes the steps of preparing one affected node, quiescing all affected servers in the node, stopping all affected servers in the node, synchronizing the node, delivering the applications or updates, starting all affected servers, reactivating all affected servers, restoring the affected node, and repeating these steps for each affected node one at a time until all targeted data processing systems have been affected." The patent application was filed on Oct. 27, 2008 (12/259,272). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,010,504.PN.&OS=PN/8,010,504&RS=PN/8,010,504 Written by Anjali Jha; edited by Jaya Anand. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1059423 (c) 2011 Targeted News Service |