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U.S. Patents Awarded to Inventors in Oregon (Aug. 24)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Aug. 24 -- The following federal patents were awarded to inventors in Oregon. *** International Business Machines Assigned Patent for System and Method for Aggregating Transmit Completion Interrupts ALEXANDRIA, Va., Aug. 23 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,006,006) developed by Xiuling Ma, Portland, Ore., for a "system and method for aggregating transmit completion interrupts." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and methods for aggregating transmit completion interrupts for multiple packets are provided. A network device can include a buffer with multiple memory locations capable of temporarily storing a packet being transmitted across the network via the network device and nodes connected to the network device. The network device can include a high watermark for determining when to process transmit completion interrupts. If the number of packets stored in the memory exceeds the high watermark, an aggregated transmit completion interrupt for all of the packets can be processed. Otherwise, the network device waits until sufficient packets are received to reach the high watermark." The patent application was filed on June 19, 2008 (12/142,385). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,006.PN.&OS=PN/8,006,006&RS=PN/8,006,006 Written by Arpi Sharma; edited by Jaya Anand. *** Intel Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Intel, Santa Clara, Calif., has been assigned a patent (8,005,976) developed by David L. Graumann, Beaverton, Ore., and Claudia M. Henry, Portland, Ore., for an "establishing optimal latency in streaming data applications that use data packets." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments for an apparatus and method are provided that can build latency in streaming applications that use data packets. In an embodiment, a system has an under-run forecasting mechanism, a statistics monitoring mechanism, and a playback queuing mechanism. The under-run forecasting mechanism determines an estimate of when a supply of data packets to convert will be exhausted. The statistics monitoring mechanism measures the arrival fluctuations of the supply of data packets. The playback queuing mechanism can build the latency." The patent application was filed on June 22, 2009 (12/489,321). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,005,976.PN.&OS=PN/8,005,976&RS=PN/8,005,976 Written by Arpi Sharma; edited by Jaya Anand. *** Autodesk Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Autodesk, San Rafael, Calif., has been assigned a patent (8,005,650) developed by four co-inventors for an "enhanced flattening for cable and wiring harnesses in computer-aided design drawings." The co-inventors are Steve Flores, Beaverton, Ore., Baolin Jiang, Shanghai, China, Wang Xianfeng, Shanghai, China, and Chengyun Yang, Shanghai, China. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the invention include a method for generating a two-dimensional (2D) flattened nailboard representation of a wiring harness in a three-dimensional (3D) computer-aided design (CAD) model. The nailboard representation invention may be used to provide a dimensionally accurate "flattened" view of a complex 3D wiring harness depicted in a CAD model, without cutting any of the wires included in the harness, and minimizing the overlap of multiple exposed wires present in wire loops." The patent application was filed on Feb. 28, 2008 (12/039,617). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,05,650.PN.&OS=PN/80,05,650&RS=PN/80,05,650 Written by Ruby Maibam; edited by Jaya Anand. *** CollegeNet Assigned Patent ALEXANDRIA, Va., Aug. 24 -- CollegeNet, Portland, Ore., has been assigned a patent (8,005,875) developed by Matthew W. Hickey, Portland, Ore., James H. Wolfston, West Linn, Ore., and Susan E. Malveau, Lake Oswego, Ore., for an "automatic data transmission in response to content of electronic forms satisfying criteria." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Automatic transmission of information is generated when the content of a posted electronic form matches a predefined criteria. An interface allows the user to create a criterion template to specify the match criterion without requiring the user to have the skills of a professional programmer. The person to be notified and the form and content of the notification can also be defined by the user and can be dependent on the content of the posted form. In one application, individuals associated with an institution of higher learning are automatically notified when a student submits an electronic profile form showing that the student meets a pre-specified criteria." The patent application was filed on Nov. 3, 2008 (12/264,042). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=80,05,875.PN.&OS=PN/80,05,875&RS=PN/80,05,875 Written by Rajat Puri; edited by Jaya Anand. *** Intel Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Intel, Santa Clara, Calif., has been assigned a patent (8,006,164) developed by five co-inventors for a "memory cell supply voltage control based on error detection." The co-inventors are Khellah Muhammad, Tigard, Ore., Dinesh Somasekhar, Portland, Ore., Yibin Ye, Portland, Ore., Nam Sung Kim, Hillsboro, Ore., and Vivek De, Beaverton, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "For one embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments have one or more other features." The patent application was filed on Sept. 29, 2006 (11/542,007). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,164&OS=8,006,164&RS=8,006,164 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** VMware Assigned Patent ALEXANDRIA, Va., Aug. 24 -- VMware, Palo Alto, Calif., has been assigned a patent (8,005,787) developed by Bruce J. Schuchardt, Newberg, Ore., for a data replication method. The abstract of the patent published by the U.S. Patent and Trademark Office states: "To ensure data consistency for a new data replica created for a computing system, the transmission and receipt of messages altering the data are monitored and replication of the data is permitted when all changes to the data that have been transmitted to the data have been received." The patent application was filed on Nov. 2, 2007 (11/982,563). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,005,787.PN.&OS=PN/8,005,787&RS=PN/8,005,787 Written by Anjali Jha; edited by Jaya Anand. *** Digimarc Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Digimarc, Beaverton, Ore., has been assigned a patent (8,005,746) developed by William Y. Conwell, Portland, Ore., for "auction methods and systems." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Known auction techniques are modified to provide various benefits. In one arrangement, a pseudo-random function is employed to determine whether a nominally-ended auction should be extended, allowing an unsuccessful remorseful bidder a possible further chance to win the auction. A variety of other features and arrangements are also detailed." The patent application was filed on April 9, 2007 (11/733,094). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,005,746.PN.&OS=PN/8,005,746&RS=PN/8,005,746 Written by Anjali Jha; edited by Jaya Anand. *** Digimarc Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Digimarc, Beaverton, Ore., has been assigned a patent (8,006,092) developed by four co-inventors for a "digital watermarks for checking authenticity of printed objects." The co-inventors are Tony F. Rodriguez, Portland, Ore., Mark E. Haynes, Manning, Ore., Hugh L. Brunk, Portland, Ore., and Geoffrey B. Rhoads, West Linn, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The invention provides methods for embedding digital watermarks for authentication of printed objects, and corresponding methods for authenticating these objects. One aspect of the invention is a method of embedding a digital watermark in a digital image to be printed on an object. The method embeds an auxiliary signal in the digital image so that the auxiliary signal is substantially imperceptible, yet machine readable. It converts the image to a halftone image using a halftoning process. If copies are made of the printed image, the image characteristics change due a change in the halftoning process used to create the copies. These changes are detected to determine whether a suspect document is authentic." The patent application was filed on July 17, 2007 (11/779,061). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,092.PN.&OS=PN/8,006,092&RS=PN/8,006,092 Written by Kusum Sangma; edited by Anand Kumar. *** Intel Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Intel, Santa Clara, Calif., has been assigned a patent (8,006,090) developed by Ned M. Smith, Beaverton, Ore., for a "system and method for combining user and platform authentication in negotiated channel security protocols." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A network security handshake exchange for combining user and platform authentication. The security handshake exchange performs operations on a pre-master secret to increase identity verification and security. The pre-master secret is augmented and authenticated with platform identity and user identity credentials of one endpoint. A second phase of exchanges may include exchange of a master secret that is the pre-master secret modified with platform identity and user identity of the other endpoint." The patent application was filed on May 19, 2009 (12/468,532). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,090.PN.&OS=PN/8,006,090&RS=PN/8,006,090 Written by Kusum Sangma; edited by Anand Kumar. *** Micron Technology Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,006,072) developed by Neal Andrew Cook, Reading, United Kingdom, Alan T. Wootton, Saratoga, Calif., and James Peterson, Portland, Ore., for a "reducing data hazards in pipelined processors to provide high processor utilization." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data." The patent application was filed on May 18, 2010 (12/782,474). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,072&OS=8,006,072&RS=8,006,072 Written by Kusum Sangma; edited by Anand Kumar. *** Intertrust Technologies Assigned Patent ALEXANDRIA, Va., Aug. 24 -- Intertrust Technologies, Sunnyvale, Calif., has been assigned a patent (8,006,087) developed by four co-inventors for "systems and methods for secure transaction management and electronic rights protection." The co-inventors are Karl L. Ginter, Beltsville, Md., Victor H. Shear, Bethesda, Md., Francis J. Spahn, El Cerrito, Calif., and David M. Van Wie, Eugene, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node. These techniques may be used to support an all-electronic information distribution, for example, utilizing the "electronic highway." The patent application was filed on Oct. 29, 2007 (11/980,282). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,087.PN.&OS=PN/8,006,087&RS=PN/8,006,087 Written by Kusum Sangma; edited by Anand Kumar. *** Intel Assigned Patent for Dynamically Reconfiguring Platform Settings ALEXANDRIA, Va., Aug. 24 -- Intel, Santa Clara, Calif., has been assigned a patent (8,006,082) developed by Arzhan I. Kinzhalin, Cordoba, Argentina, Mario Bertogna, Cordoba, Argentina, and Ricardo Morin, Portland, Ore., for a "dynamically reconfiguring platform settings." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, a system may receive a pattern from an analysis engine, where the pattern includes information regarding a corrective action to be taken on a configuration setting of a processor, configure a performance monitor based on the pattern, collect performance monitoring information during program operation, analyze the information during the program operation, and dynamically implement the corrective action during the program operation based on the analysis. Other embodiments are described and claimed." The patent application was filed on Sept. 29, 2008 (12/286,225). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,082.PN.&OS=PN/8,006,082&RS=PN/8,006,082 Written by Kusum Sangma; edited by Anand Kumar. *** Intel Assigned Patent for Thread Migration Control Based on Prediction of Migration Overhead ALEXANDRIA, Va., Aug. 24 -- Intel, Santa Clara, Calif., has been assigned a patent (8,006,077) developed by Tong Li, Hillsboro, Ore., Daniel Baumberger, Cornelius, Ore., and Scott Hahn, Beaverton, Ore., for a "thread migration control based on prediction of migration overhead." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A processing system features a first processing core to operate in a first node, a second processing core to operate in a second node, and random access memory (RAM) responsive to the first and second processing cores. The processing system also features control logic to perform operations such as (a) automatically updating a resident set size (RSS) counter to correspond to the RSS for the thread on the first node in response to allocation of a page frame for a thread in the first node, and (b) using the RSS counter to predict migration overhead when determining whether the thread should be migrated from the first processing core to the second processing core. Other embodiments are described and claimed." The patent application was filed on March 29, 2007 (11/731,276). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,006,077.PN.&OS=PN/8,006,077&RS=PN/8,006,077 Written by Kusum Sangma; edited by Anand Kumar. *** Intel Assigned Patent for Stream Priority ALEXANDRIA, Va., Aug. 24 -- Intel, Santa Clara, Calif., has been assigned a patent (8,006,017) developed by five co-inventors for a stream priority. The co-inventors are William T. Futral, Portland, Ore., Kenneth C. Creta, Gig Harbor, Wash., Sujoy Sen, Portland, Ore., Gregory D. Cummings, Portland, Ore., and Sivakumar Radhakrishnan, Portland, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction." The patent application was filed on Dec. 21, 2004 (11/020,500). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8006017.PN.&OS=PN/8006017&RS=PN/8006017 Written by Kusum Sangma; edited by Anand Kumar. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1058745 (c) 2011 Targeted News Service |