TMCnet News
U.S. Patents Awarded to Inventors in California (July 20)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., July 20 -- The following federal patents were awarded to inventors in California. *** Nestec Assigned Patent ALEXANDRIA, Va., July 19 -- Nestec, Vevey, Switzerland, has been assigned a patent (D641,620) developed by Richard T. Hammond, Los Angeles, Janet T. Planet, Glendale, Calif., and Spencer MacKay, Burbank, Calif., for an ornamental design for a box assembly. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for a box assembly, as shown and described." The patent application was filed on Aug. 19, 2009 (D/342,155). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,620.PN.&OS=PN/D641,620&RS=PN/D641,620 Written by Arpi Sharma; edited by Jaya Anand. *** California Inventor Develops Patent for Ladies Wrap ALEXANDRIA, Va., July 19 -- Sophonia A. Shield, Whittier, Calif., has been issued a patent (D641,542) for an ornamental design for ladies wrap. The patent application was filed on July 17, 2009 (D/340,441). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,542.PN.&OS=PN/D641,542&RS=PN/D641,542 Written by Arpi Sharma; edited by Jaya Anand. *** Intertrust Technologies Assigned Patent ALEXANDRIA, Va., July 19 -- Intertrust Technologies, Sunnyvale, Calif., has been assigned a patent (7,984,509) developed by four co-inventors for "systems and methods for secure transaction management and electronic rights protection." The co-inventors are Karl L. Ginter, Beltsville, Md., Victor H. Shear, Bethesda, Md., Francis J. Spahn, El Cerrito, Calif., and David M. Van Wie, Sunnyvale, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention provides systems and methods for secure transaction management and electronic rights protection. Electronic appliances such as computers equipped in accordance with the present invention help to ensure that information is accessed and used only in authorized ways, and maintain the integrity, availability, and/or confidentiality of the information. Such electronic appliances provide a distributed virtual distribution environment (VDE) that may enforce a secure chain of handling and control, for example, to control and/or meter or otherwise monitor use of electronically stored or disseminated information. Such a virtual distribution environment may be used to protect rights of various participants in electronic commerce and other electronic or electronic-facilitated transactions. Distributed and other operating systems, environments and architectures, such as, for example, those using tamper-resistant hardware-based processors, may establish security at each node. These techniques may be used to support an all-electronic information distribution, for example, utilizing the "electronic highway."" The patent application was filed on May 25, 2007 (11/807,313). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,984,509.PN.&OS=PN/7,984,509&RS=PN/7,984,509 Written by Arpi Sharma; edited by Jaya Anand. *** California Inventor Develops Patent for Cutting Board ALEXANDRIA, Va., July 19 -- Paul R. Hashim, Bakersfield, Calif., has been issued a patent (D641,598) for an ornamental design for a cutting board. The patent application was filed on Dec. 10, 2007 (D/290,482). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,598.PN.&OS=PN/D641,598&RS=PN/D641,598 Written by Arpi Sharma; edited by Jaya Anand. *** 101 Holdings Assigned Patent ALEXANDRIA, Va., July 19 -- 101 Holdings, Solana Beach, Calif., has been assigned a patent (D641,546) developed by Sung Choi, Los Angeles, for an ornamental design for a shoe. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for a shoe, as shown and described." The patent application was filed on Aug. 7, 2009 (D/341,553). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,546.PN.&OS=PN/D641,546&RS=PN/D641,546 Written by Arpi Sharma; edited by Jaya Anand. *** Adobe Systems Assigned Patent ALEXANDRIA, Va., July 19 -- Adobe Systems, San Jose, Calif., has been assigned a patent (7,984,514) developed by Deneb Meketa, San Francisco, for a "secure operation of transitory computer applications." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A security application is described for determining conditions within a computer application that would create the desire to allow or disallow access to certain system functions or features by the application. The security application analyzes the conditions and sets a lock that enables the application to perform only certain types of actions that would be considered secure by the security application." The patent application was filed on July 10, 2006 (11/483,792). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,984,514.PN.&OS=PN/7,984,514&RS=PN/7,984,514 Written by Arpi Sharma; edited by Jaya Anand. *** ENcomfort Designs Assigned Patent ALEXANDRIA, Va., July 19 -- ENcomfort Designs, San Diego, has been assigned a patent (D641,563) developed by Nick Matteson, San Diego, and Erick Pearson, San Diego, for an ornamental design for a collapsible backrest. The abstract of the patent published by the U.S. Patent and Trademark Office states: "We claim the ornamental design for a collapsible backrest, as shown and described." The patent application was filed on Dec. 8, 2009 (D/351,621). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,563.PN.&OS=PN/D641,563&RS=PN/D641,563 Written by Arpi Sharma; edited by Jaya Anand. *** Rovi Solutions Assigned Patent ALEXANDRIA, Va., July 19 -- Rovi Solutions, Santa Clara, Calif., has been assigned a patent (7,984,511) developed by six co-inventors for a self-protecting digital content. The co-inventors are Paul Carl Kocher, San Francisco, Joshua Michael Jaffe, San Francisco, Benjamin Che-Ming Jun, Oakland, Calif., Carter Cyrus Laren, San Leandro, Calif., Peter Kelley Pearson, Aptos, Calif., and Nathaniel James Lawson, Oakland, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Technologies are disclosed to transfer responsibility and control over security from player makers to content authors by enabling integration of security logic and content. An exemplary optical disc carries an encrypted digital video title combined with data processing operations that implement the title's security policies and decryption processes. Player devices include a processing environment (e.g., a real-time virtual machine), which plays content by interpreting its processing operations. Players also provide procedure calls to enable content code to load data from media, perform network communications, determine playback environment configurations, access secure nonvolatile storage, submit data to CODECs for output, and/or perform cryptographic operations. Content can insert forensic watermarks in decoded output for tracing pirate copies. If pirates compromise a player or title, future content can be mastered with security features that, for example, block the attack, revoke pirated media, or use native code to correct player vulnerabilities." The patent application was filed on Oct. 31, 2007 (11/981,990). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,984,511.PN.&OS=PN/7,984,511&RS=PN/7,984,511 Written by Arpi Sharma; edited by Jaya Anand. *** California Inventor Develops Patent for Beverage Can Holder ALEXANDRIA, Va., July 19 -- Mario Fiumani, Glendale, Calif., has been issued a patent (D641,593) for an ornamental design for a beverage can holder. The patent application was filed on Nov. 11, 2010 (D/378,956). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,593.PN.&OS=PN/D641,593&RS=PN/D641,593 Written by Arpi Sharma; edited by Jaya Anand. *** SCA Hygiene Products Assigned Patent ALEXANDRIA, Va., July 19 -- SCA Hygiene Products, Gothenburg, Sweden, has been assigned a patent (D641,578) developed by Thomas Meyerhoffer, Montara, Calif., for an ornamental design for a paper towel dispenser. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for a paper towel dispenser, as shown and described." The patent application was filed on Dec. 29, 2010 (D/382,088). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,578.PN.&OS=PN/D641,578&RS=PN/D641,578 Written by Arpi Sharma; edited by Jaya Anand. *** YSN Imports Assigned Patent ALEXANDRIA, Va., July 19 -- YSN Imports, Gardena, Calif., has been assigned a patent (D641,555) developed by Yisroel Ovadyah Schochet, Los Angeles, for an ornamental design for a BBQ grill brush. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for a BBQ grill brush, as shown and described." The patent application was filed on March 30, 2011 (D/388,592). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,555.PN.&OS=PN/D641,555&RS=PN/D641,555 Written by Arpi Sharma; edited by Jaya Anand. *** Procter & Gamble Assigned Patent ALEXANDRIA, Va., July 19 -- Procter & Gamble, Cincinnati, has been assigned a patent (D641,635) developed by seven co-inventors for an ornamental design for a "container for hair care composition." The co-inventors are Janelle Yurong Wang Treadway, Whittier, Calif., Marc Christopher Hatcher, Milford, Ohio, Graham Hufton, New York, Ian Andrew Carnduff, New York, Paul F. Diehl, Brooklyn, N.Y., Akina Kurihara, New York, and Douglas Scott Miller, Lebanon, Ohio. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for a container for hair care composition, as shown and described." The patent application was filed on May 15, 2009 (D/337,151). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,635.PN.&OS=PN/D641,635&RS=PN/D641,635 Written by Arpi Sharma; edited by Jaya Anand. *** Rock Fit Assigned Patent ALEXANDRIA, Va., July 19 -- Rock Fit, Commerce, Calif., has been assigned a patent (D641,539) developed by Frank Zarabi, Commerce, Calif., for an ornamental design for a supportive apparel. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for supportive apparel, as shown and described." The patent application was filed on May 21, 2010 (D/362,278). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,539.PN.&OS=PN/D641,539&RS=PN/D641,539 Written by Arpi Sharma; edited by Jaya Anand. *** Caitin Assigned Patent ALEXANDRIA, Va., July 19 -- Caitin, Fremont, Calif., has been assigned a patent (7,980,271) developed by Jayden David Harman, San Rafael, Calif., for a fluid flow controller. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A fluid pathway is provided with a flow controller in at least a portion of its length wherein the flow controller comprises an active surface capable of influencing the fluid flow through the fluid pathway, the configuration of the active surface conforming to at least one logarithmic curve conforming to the Golden Section." The patent application was filed on June 30, 2004 (10/882,412). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,980,271&OS=7,980,271&RS=7,980,271 Written by Arpi Sharma; edited by Jaya Anand. *** Meyer Intellectual Properties Assigned Patent ALEXANDRIA, Va., July 19 -- Meyer Intellectual Properties, British Virgin Islands, has been assigned a patent (D641,585) developed by Stanley Kin Sui Cheng, Vallejo, Calif., for an ornamental design for a cookware vessel. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for a cookware vessel, as shown and described." The patent application was filed on May 3, 2007 (D/279,606). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,585.PN.&OS=PN/D641,585&RS=PN/D641,585 Written by Arpi Sharma; edited by Jaya Anand. *** SHURflo Assigned Patent ALEXANDRIA, Va., July 19 -- SHURflo, Cypress, Calif., has been assigned a patent (7,980,270) developed by Paul H. Bertsch, Huntington Beach, Calif., Christopher J. Taylor-McCune, Mission Viejo, Calif., and Christopher H. Verdugo, Yorba Linda, Calif., for a "spool valve apparatus and method." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Some embodiments of the present invention provide a spool valve having a spool axially movable within a sleeve of two or more stacked rings having projections extending therebetween. One or more seals on the spool can slide across surfaces of the stacked rings in movement of the spool to different positions corresponding to different states of the valve. In some embodiments, one or more of the stacked rings can have projections extending toward and contacting an adjacent ring of the sleeve, thereby maintaining desired axial positions of the rings relative to one another while providing apertures through which fluid can flow and supporting surfaces for each seal as it slides from one ring to another." The patent application was filed on May 12, 2005 (11/127,796). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,980,270&OS=7,980,270&RS=7,980,270 Written by Arpi Sharma; edited by Jaya Anand. *** Hewlett-Packard Development Assigned Patent ALEXANDRIA, Va., July 20 -- Hewlett-Packard Development, Houston, has been assigned a patent (7,984,283) developed by Eric Peacock, Sunnyville, Calif., and John J. Youden, San Jose, Calif., for a "system and method for secure operating system boot." The abstract of the patent published by the U.S. Patent and Trademark Office states: "There is provided a method for operating a basic input/output system (BIOS) of a pay-as-you go computer system. In one example embodiment, the method includes determining if a user password feature is activated on a hard drive and computing a password to unlock the hard drive if the password feature is activated. In another example embodiment, the method includes performing a checksum verification of boot information. In yet another example embodiment, the method includes storing portions of boot information in non-standard locations on the hard drive and combining the portions using operators." The patent application was filed on Oct. 31, 2006 (11/590,227). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,283.PN.&OS=PN/79,84,283&RS=PN/79,84,283 Written by Ruby Maibam; edited by Jaya Anand. *** California Inventors Develop Patent for System and Method of Instruction Modification ALEXANDRIA, Va., July 20 -- John Banning, Sunnyvale, Calif., Eric Hao, Cupertino, Calif., and Brett Coon, Milpitas, Calif., have developed a patent (7,984,277) for a "system and method of instruction modification." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern." The patent application was filed on Feb. 2, 2010 (12/698,809). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,277.PN.&OS=PN/79,84,277&RS=PN/79,84,277 Written by Ruby Maibam; edited by Jaya Anand. *** NetLogic Microsystems Assigned Patent ALEXANDRIA, Va., July 20 -- NetLogic Microsystems, Santa Clara, Calif., has been assigned a patent (7,984,268) developed by David T. Hass, Santa Clara, Calif., and Abbas Rashid, Fremont, Calif., for an "advanced processor scheduling in a multithreaded system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner." The patent application was filed on July 23, 2004 (10/898,007). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,268.PN.&OS=PN/79,84,268&RS=PN/79,84,268 Written by Ruby Maibam; edited by Jaya Anand. *** Spansion Assigned Patent ALEXANDRIA, Va., July 20 -- Spansion, Sunnyvale, Calif., has been assigned a patent (7,984,284) developed by Anthony Le, San Jose, Calif., and Jackson Huang, San Jose, Calif., for an SPI auto-boot mode. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and methods of detecting an auto-boot mode and booting data from a serial peripheral interface to a processor without the need of a read instruction utilizing a serial peripheral interface having an auto-boot mode detector are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to serially communicate data between the processor and at least two peripherals, and an auto-boot component operably coupled to the serial processing component, comprising an auto-boot mode detector configured to determine whether a boot mode exists based on detecting whether serial input data is received during a predetermined wait state, and configured to selectively boot data to a start address associated with the processor based on the boot mode determination." The patent application was filed on Nov. 27, 2007 (11/945,316). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,284.PN.&OS=PN/79,84,284&RS=PN/79,84,284 Written by Ruby Maibam; edited by Jaya Anand. *** Intel, Forsyth, Abrash Assigned Patent ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., Tom Forsyth, Kirkland, Wash., and Michael Abrash, Kirkland, Wash., have been assigned a patent (7,984,273) developed by five co-inventors for a "system and method for using a mask register to track progress of gathering elements from memory." The co-inventors are Eric Sprangle, Austin, Texas, Anwar Rohillah, Austin, Texas, Robert Cavin, San Francisco, Tom Forsyth, Kirkland, Wash., and Michael Abrash, Kirkland, Wash. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed." The patent application was filed on Dec. 31, 2007 (11/967,482). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,273.PN.&OS=PN/79,84,273&RS=PN/79,84,273 Written by Ruby Maibam; edited by Jaya Anand. *** Invention Science Fund I Assigned Patent ALEXANDRIA, Va., July 20 -- Invention Science Fund I, Bellevue, Wash., has been assigned a patent (7,984,278) developed by five co-inventors for a "hardware resource having an optimistic policy and a pessimistic policy." The co-inventors are Bran Ferren, Beverly Hills, Calif., W. Daniel Hillis, Encino, Calif., Nathan P. Myhrvold, Medina, Wash., Clarence T. Tegreene, Bellevue, Wash., and Lowell L. Wood Jr., Bellevue, Wash. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource management policy and a second execution of one or more instructions pursuant to a pessimistic resource management policy, the optimistic resource management policy assuming that less than an optimistic level of at least one error will occur during the first execution, and the pessimistic resource management policy assuming that greater than a pessimistic level of the at least one error will occur during the second execution. Based at least partially on the comparison, the resource manager selects a resource management policy from between the optimistic and pessimistic resource management policies, and associates the selected resource management policy with the one or more instructions." The patent application was filed on May 19, 2009 (12/454,633). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,278.PN.&OS=PN/79,84,278&RS=PN/79,84,278 Written by Ruby Maibam; edited by Jaya Anand. *** VNS Portfolio Assigned Patent ALEXANDRIA, Va., July 20 -- VNS Portfolio, Cupertino, Calif., has been assigned a patent (7,984,266) developed by Charles H. Moore, Sierra City, Calif., for an "integrated computer array with independent functional configurations." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A computer array (10) has a plurality of computers (12) for accomplishing a larger task that is divided into smaller tasks, each of the smaller tasks being assigned to one or more of the computers (12). Each of the computers (12) may be configured for specific functions and individual input/output circuits (26) associated with exterior computers (12) are specifically adapted for particular input/output functions. An example of 25 computers (12) arranged in the computer array (10) has a centralized computational core (34) with the computers (12) nearer the edge of the die (14) being configured for input and/or output." The patent application was filed on June 5, 2007 (11/810,183). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,266.PN.&OS=PN/79,84,266&RS=PN/79,84,266 Written by Ruby Maibam; edited by Jaya Anand. *** Apple Assigned Patent ALEXANDRIA, Va., July 20 -- Apple, Cupertino, Calif., has been assigned a patent (7,984,274) developed by Sudarshan Kadambi, Sunnyvale, Calif., Po-Yung Chang, Saratoga, Calif., and Eric Hao, Cupertino, Calif., for a "partial load/store forward prediction." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event during execution. A PSTLF event occurs if a plurality of bytes, accessed responsive to the first load instruction during execution, include at least a first byte updated responsive to a previous uncommitted store operation and also include at least a second byte not updated responsive to the previous uncommitted store operation. Coupled to receive the first load instruction, the circuit is configured to generate one or more load operations responsive to the first load instruction. The load operations are to be executed in the processor to execute the first load instruction, and a number of the load operations is dependent on the prediction by the prediction circuit." The patent application was filed on June 18, 2009 (12/486,917). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,274.PN.&OS=PN/79,84,274&RS=PN/79,84,274 Written by Ruby Maibam; edited by Jaya Anand. *** Juniper Networks Assigned Patent ALEXANDRIA, Va., July 20 -- Juniper Networks, Sunnyvale, Calif., has been assigned a patent (7,984,235) developed by four co-inventors for a "reducing content addressable memory (CAM) power consumption counters." The co-inventors are Harsha Narayan, Sunnyvale, Calif., Kenneth Huang, San Jose, Calif., Ruturaj Pathak, Fremont, Calif., and Soren B. Pendersen, Petaluma, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method may include counting the number of times each of a plurality of entries in a content addressable memory (CAM) matches one or more searches; grouping entries in the CAM into a first subset and a second subset based on the number of times each of the plurality of entries in the CAM matches one or more searches; and searching the first subset for a matching entry and, if no matching entry is found, searching the second subset for the matching entry." The patent application was filed on Jan. 29, 2010 (12/697,063). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,235.PN.&OS=PN/79,84,235&RS=PN/79,84,235 Written by Ruby Maibam; edited by Jaya Anand. *** Intel Assigned Patent for Method and Apparatus for Supporting Scalable Coherence on Many-core Products Through Restricted Exposure ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., has been assigned a patent (7,984,244) developed by Joshua B. Fryman, Sunnyvale, Calif., Mohan Rajagopalan, Mountain View, Calif., and Anwar Ghuloum, Menlo Park, Calif., for a "method and apparatus for supporting scalable coherence on many-core products through restricted exposure." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed." The patent application was filed on Dec. 28, 2007 (12/005,785). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,244.PN.&OS=PN/79,84,244&RS=PN/79,84,244 Written by Ruby Maibam; edited by Jaya Anand. *** EMC Assigned Patent ALEXANDRIA, Va., July 20 -- EMC, Hopkinton, Mass., has been assigned a patent (7,984,255) developed by Mandavilli Navneeth Rao, Mountain View, Calif., for "optimizing reclamation of data space." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An amount of storage to reclaim is determined based at least in part on a write size of new previous version data written most recently to a data region. The determined amount of storage is reclaimed." The patent application was filed on March 16, 2009 (12/381,888). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,255.PN.&OS=PN/79,84,255&RS=PN/79,84,255 Written by Ruby Maibam; edited by Jaya Anand. *** VMware Assigned Patent for Method and System for Generating Consistent Snapshots for a Group of Data Objects ALEXANDRIA, Va., July 20 -- VMware, Palo Alto, Calif., has been assigned a patent (7,984,254) developed by Christos Karamanolis, Los Gatos, Calif., Matthew Benjamin Amdur, Cambridge, Mass., and Patrick William Penzias Dirks, Monte Sereno, Calif., for a "method and system for generating consistent snapshots for a group of data objects." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Snapshots that are consistent across a group of data objects are generated. The snapshots are initiated by a coordinator, which transmits a sequence of commands to each storage node hosting a data object within a group of data objects. The first command prepares a data object for a snapshot. After a data object has been successfully prepared, an acknowledgment is sent to the coordinator. Once all appropriate acknowledgments are received, the coordinator sends a command to confirm that a snapshot has been created for each data object in the respective group. After receiving this confirmation, the coordinator takes action to confirm or record the successful completion of the group-consistent snapshot." The patent application was filed on April 4, 2008 (12/098,116). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,254.PN.&OS=PN/79,84,254&RS=PN/79,84,254 Written by Ruby Maibam; edited by Jaya Anand. *** Marvell International Assigned Patent for Multicore Memory Management System ALEXANDRIA, Va., July 20 -- Marvell International, Bermuda, has been assigned a patent (7,984,246) developed by Geoffrey K. Yung, Belmont, Calif., and Chia-Hung Chien, Sunnyvale, Calif., for a "multicore memory management system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal." The patent application was filed on April 7, 2010 (12/755,893). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,246.PN.&OS=PN/79,84,246&RS=PN/79,84,246 Written by Ruby Maibam; edited by Jaya Anand. *** Hewlett-Packard Development Assigned Patent ALEXANDRIA, Va., July 20 -- Hewlett-Packard Development, Houston, has been assigned a patent (7,984,147) developed by Raja Daoud, Santa Clara, Calif., and Francisco J. Romero, Plano, Texas, for an "apparatus and method for identifying a requested level of service for a transaction." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An apparatus for identifying a requested level of service for a transaction wherein the transaction may be processed in accordance with the requested level of service. The invention is preferably embodied in computer readable program code stored in suitable storage media, and comprises, program code for selecting the requested level of service for the transaction, and program code for assigning the requested level of service to the transaction. The transaction is preferably a packetized signal comprising at least a data packet having a service tag associated therewith, wherein the service tag includes the requested level of service. The requested level of service can be any suitable factors or combination thereof, and can be assigned at any point on the network. The service tag is read from the transaction using suitable program code (e.g., at a load balancer), and based on the requested level of service, the transaction is directed to and processed by a network device that is best able to provide the requested level of service." The patent application was filed on Dec. 29, 2000 (09/751,009). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7984147.PN.&OS=PN/7984147&RS=PN/7984147 Written by Ankresh Ranjan; edited by Jaya Anand. *** NetApp Assigned Patent ALEXANDRIA, Va., July 20 -- NetApp, Sunnyvale, Calif., has been assigned a patent (7,984,259) developed by Robert M. English, Menlo Park, Calif., for "reducing load imbalance in a storage system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention provides a system, method, and computer program product for reducing load imbalance in a storage system having a plurality of storage devices organized in one or more RAIDs for storing data by moving data from heavily-loaded storage devices to less-loaded storage devices during normal data access operations. As a result of moving data to less-loaded storage devices, the service latency of those storage devices decreases, thereby optimizing the system's performance." The patent application was filed on Dec. 17, 2007 (11/957,925). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,259.PN.&OS=PN/79,84,259&RS=PN/79,84,259 Written by Ruby Maibam; edited by Jaya Anand. *** Marvell International Assigned Patent ALEXANDRIA, Va., July 20 -- Marvell International, Hamilton, Bermuda, has been assigned a patent (7,984,252) developed by Leon A. Krantz, Mission Viejo, Calif., Kha Nguyen, Anaheim, Calif., and Michael J. North, Orange, Calif., for a "storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A controller including an interface module and an index module. The interface module is configured to connect devices. The index module is configured to include, in a table stored in memory, an entry for each of the devices. Each entry includes an address field. The index module is configured to: receive a frame of data including an address of one of the devices; compare the address to the address fields associated with the entries in the table; in response to the address matching one of the address fields, access an index value identifying an entry of the table when the address matches one of the address fields; and in response to the address not matching one of the address fields, generate the index value. The index value is used to connect the device associated with the matching one of the address fields with the one of the devices." The patent application was filed on July 9, 2010 (12/833,026). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,252.PN.&OS=PN/79,84,252&RS=PN/79,84,252 Written by Ruby Maibam; edited by Jaya Anand. *** Hewlett-Packard Development Assigned Patent for Program Thread Syncronization ALEXANDRIA, Va., July 20 -- Hewlett-Packard Development, Houston, has been assigned a patent (7,984,242) developed by Jean-Francois C. P. Collard, Sunnyvale, Calif., Norman Paul Jouppi, Palo Alto, Calif., and Michael S. Schlansker, Los Altos, Calif. for program thread syncronization. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized." The patent application was filed on June 1, 2009 (12/476,109). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,242.PN.&OS=PN/79,84,242&RS=PN/79,84,242 Written by Ruby Maibam; edited by Jaya Anand. *** Oracle America Assigned Patent ALEXANDRIA, Va., July 20 -- Oracle America, Redwood City, Calif., has been assigned a patent (7,984,265) developed by Wei Chung Hsu, Inver Grove Heights, Minn., and Yuan C. Chou, Los Gatos, Calif., for an "event address register history buffers for supporting profile-guided and dynamic optimizations." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A computer processor and a method of using the computer processor take advantage of information in the event address register of the computer processor by saving information from the event address register to an event address register history buffer. Thus, the event address register history buffer includes a cluster of events associated with execution of a computer program. The cluster of events is analyzed and the computer program modified, either statically or dynamically, to eliminate or at least ameliorate the effects of such events in further execution of the computer program." The patent application was filed on May 16, 2008 (12/152,727). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,265.PN.&OS=PN/79,84,265&RS=PN/79,84,265 Written by Ruby Maibam; edited by Jaya Anand. *** Cisco Technology Assigned Patent for Network Response Time Measurements in Asymmetric Routing Environment ALEXANDRIA, Va., July 20 -- Cisco Technology, San Jose, Calif., has been assigned a patent (7,984,140) developed by Ulrica De Fort-Menares, San Carlos, Calif., and Benoit Claise, Crisnee, Belgium, for a "network response time measurements in an asymmetric routing environment." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, a method can include: (i) receiving flow records from a plurality of network devices on asymmetric paths; (ii) reconstructing a network transaction from the received flow records; and (iii) deriving response times using the reconstructed network transaction." The patent application was filed on March 14, 2007 (11/717,932). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7984140.PN.&OS=PN/7984140&RS=PN/7984140 Written by Ankresh Ranjan; edited by Jaya Anand. *** Intel Assigned Patent ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., has been assigned a patent (7,984,248) developed by Sailesh Kottapalli, San Jose, Calif., John H. Crawford, Saratoga, Calif., and Kushagra Vaid, San Jose, Calif., for a "transaction based shared data operations in a multiprocessor environment." The abstract of the patent published by the U.S. Patent and Trademark Office states: "The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores." The patent application was filed on Dec. 29, 2004 (11/027,623). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,248.PN.&OS=PN/79,84,248&RS=PN/79,84,248 Written by Ruby Maibam; edited by Jaya Anand. *** VMware Assigned Patent ALEXANDRIA, Va., July 20 -- VMware, Palo Alto, Calif., has been assigned a patent (7,984,264) developed by Pratap Subrahmanyam, Saratoga, Calif., and Garrett Smith, Palo Alto, Calif., for "maintaining reverse mappings in a virtualized computer system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "For a virtual memory of a virtualized computer system in which a virtual page is mapped to a guest physical page which is backed by a machine page and in which a shadow page table entry directly maps the virtual page to the machine page, reverse mappings of guest physical pages are optimized by removing the reverse mappings of certain immutable guest physical pages. An immutable guest physical memory page is identified, and existing reverse mappings corresponding to the immutable guest physical page are removed. New reverse mappings corresponding to the identified immutable guest physical page are no longer added." The patent application was filed on Nov. 6, 2009 (12/613,922). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,264.PN.&OS=PN/79,84,264&RS=PN/79,84,264 Written by Ruby Maibam; edited by Jaya Anand. *** Google Assigned Patent ALEXANDRIA, Va., July 20 -- Google, Mountain View, Calif., has been assigned a patent (7,984,151) developed by five co-inventors for a "determining placement of user data to optimize resource utilization for distributed systems." The co-inventors are Danny Raz, Palo Alto, Calif., Nareshkumar Rajkumar, San Jose, Calif., Leeann Bent, Santa Clara, Calif., Bradley Whitehead, Mountain View, Calif., and Douglas Zongker, Palo Alto, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "User information describing a group of users of a distributed computer system configured to store and retrieve individualized user data associated with individual ones of the group of users, and system resource information associated with the distributed computer system, may be obtained. A global distribution plan describing a distribution of at least a portion of the individualized user data associated with the group may be determined based on a global optimization function of the obtained user information and system resource information associated with the distributed computer system, wherein the global optimization function is based on optimizing a global distribution of the portion of the individualized user data based on a determination of a measure of performance and fault tolerance associated with a model of the distributed computer system configured in accordance with the global distribution plan. The determined global distribution plan may be provided to a device for processing." The patent application was filed on Oct. 9, 2008 (12/248,863). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7984151.PN.&OS=PN/7984151&RS=PN/7984151 Written by Ankresh Ranjan; edited by Jaya Anand. *** Broadcom Assigned Patent ALEXANDRIA, Va., July 20 -- Broadcom, Irvine, Calif., has been assigned a patent (7,984,216) developed by four co-inventors for a "method and system for a RFIC master." The co-inventors are Frederic Hayem, San Diego, Andrew du Preez, San Diego, Louis Botha, San Diego, and Johan (Hendrik) Conroy, San Diego. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index." The patent application was filed on Aug. 18, 2009 (12/543,008). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,216.PN.&OS=PN/79,84,216&RS=PN/79,84,216 Written by Ruby Maibam; edited by Jaya Anand. *** Hewlett-Packard Development Assigned Patent ALEXANDRIA, Va., July 20 -- Hewlett-Packard Development, Houston, has been assigned a patent (7,984,485) developed by Bindu R. Rao, Laguna Niguel, Calif., and Vivek Kapadekar, Laguna Niguel, Calif, for an "ingestion interface for transferring update package containers into a distribution network." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Aspects of the present invention may be seen in a method and system for the ingestion of update package containers (or other types of containers, in general) into a distribution network. In an embodiment of the present invention, update package containers (UPC) from several different sources may be transferred into a distribution network such as a carrier network via a standardized SOAP interface. A logical repository may be assumed to exist in the distribution network. A standardized interface to such a logical repository may facilitate the integration of ingestion methods from several software originators into such a distribution network." The patent application was filed on Jan. 31, 2005 (11/047,212). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,485&OS=79,84,485&RS=79,84,485 Written by Rajat Puri; edited by Jaya Anand. *** Quartics Assigned Patent ALEXANDRIA, Va., July 20 -- Quartics, Irvine, Calif., has been assigned a patent (7,984,474) developed by Sherjil Ahmed, Irvine, Calif., and Imtinan Elahi, Richardson, Texas, for a "method and apparatus for a digitized CATV network for bundled services." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A cost-efficient digital CATV network to improve signal quality, provide reliability, and offer the ability to meet demands for interactive services is described. Analog or digital video downstream channels are converted to a digital format by a digital headend transmitter. Relatively costly error-encoding for digital video channels is also part of the digital headend transmitter. Downstream analog and digital video channels in the digital format are transmitted using time-division multiplex technology from a headend to nodes using standard network protocols, such as SONET. Standard network protocols provide error-monitoring and status indication of transmit data, thus ensuring high signal quality and reliability. Time-division multiplexing facilitates easy adding or dropping of information to a transmit path. Flexibility to add or drop information is critical in providing interactive services. Data from interactive services can be added or dropped at points of presence throughout the digital CATV network. Subscribers to the digital CATV network can communicate with each other. A digital node transmitter receives the analog or digital video channels in digital format and converts the analog or digital video channels into an analog format. The digital node transmitter also frequency-division multiplexes multiple analog or digital video channels into one analog broadband signal for broadcast to subscribers' homes." The patent application was filed on Dec. 9, 2002 (10/314,873). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,474&OS=79,84,474&RS=79,84,474 Written by Rajat Puri; edited by Jaya Anand. *** KTech Telecommunications Assigned Patent ALEXANDRIA, Va., July 20 -- KTech Telecommunications, Chatsworth, Calif., has been assigned a patent (7,984,469) developed by Steve Kuh, Northridge, Calif., for a "digital television translator with PSIP update." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A digital television translator includes a digital television receiver for receiving a first digital television signal at a first frequency and generating a digital transport stream from the first digital television signal. The digital transport stream can include original Program and System Information (PSIP) data having RX channel data that is indicative of the first frequency, the first major channel number, and/or the first minor channel number. The digital television translator also includes a PSIP update module for updating the original PSIP data in the digital transport stream by replacing the RX channel data with TX channel data. The TX data is indicative of a second frequency, a second major channel number, and/or a second minor channel number. The digital television translator further includes a digital television modulator for converting the digital transport stream having the updated PSIP data into a second digital television signal at the second frequency, where the second frequency can be the same or different from the first frequency." The patent application was filed on May 10, 2010 (12/777,108). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,469&OS=79,84,469&RS=79,84,469 Written by Rajat Puri; edited by Jaya Anand. *** Google Assigned Patent ALEXANDRIA, Va., July 20 -- Google, Mountain View, Calif., has been assigned a patent (7,984,484) developed by Brian D. Rakowski, Menlo Park, Calif., and Darick M. Tong, Palo Alto, Calif., for a "system and method for assisting in remote message server configuration." The abstract of the patent published by the U.S. Patent and Trademark Office states: "When a user enters an email address associated with a remote message server account in a configuration area on a display, one or more suggestions for other field inputs are made based on canonical data or historical data from a variety of users. If the user cannot find a desired entry in the suggestions, the user may enter new information. The newly entered information (once validated) improves the prediction capability for subsequent users. A database stores information associated with each email address domain name including one or more remote message server names, one or more username patterns and ranking values. When more than one suggestion for a field is presented to a user, the suggestions are ranked in accordance with the respective ranking values such as by the popularity of a particular configuration." The patent application was filed on Nov. 11, 2004 (10/987,125). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,484&OS=79,84,484&RS=79,84,484 Written by Rajat Puri; edited by Jaya Anand. *** Intuit Assigned Patent ALEXANDRIA, Va., July 20 -- Intuit, Mountain View, Calif., has been assigned a patent (7,984,436) developed by Calum Murray, Santa Rosa, Calif., for a "management of compatibility of software products installed on a user's computing device." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Physical components that share common attributes in a software product are combined into logical groupings. A product matrix also lists logical groupings that are included into each software product listed in the product matrix. A compatibility matrix indicates whether any two logical groupings listed in the product matrix are compatible. When a new product is provided for an installation, the compatibility matrix is consulted to determine whether any two logical groupings of the new product and installed product are compatible. An installation can proceed or be terminated based on the compatibility determination." The patent application was filed on Sept. 27, 2005 (11/236,942). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,436&OS=79,84,436&RS=79,84,436 Written by Rajat Puri; edited by Jaya Anand. *** Altera Assigned Patent ALEXANDRIA, Va., July 20 -- Altera, San Jose, Calif., has been assigned a patent (7,984,434) developed by Yogesh Gathoo, Santa Clara, Calif., for a nondestructive patching mechanism. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques and mechanisms are provided for patching software, such as software for implementing parameterizable processor cores and peripherals on a programmable chip. Software components constructed using various shared modules can be updated without affecting other components using the same shared modules. In one example, a software component includes a manifest for identifying the implementations that should be associated with the various modules. When a patched implementation is provided for a particular module, the component manifest is changed to associate the patched implementation with the component. The pre-patch implementation is preserved so that other components using the pre-patch implementation may be kept unchanged." The patent application was filed on May 21, 2003 (10/443,661). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,434.PN.&OS=PN/79,84,434&RS=PN/79,84,434 Written by Rajat Puri; edited by Jaya Anand. *** Intel Assigned Patent ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., has been assigned a patent (7,984,431) developed by four co-inventors for a "method and apparatus for exploiting thread-level parallelism." The co-inventors are Arun Kejariwal, Irvine, Calif., Xinmin Tian, Union City, Calif., Wei Li, Redwood Shores, Calif., and Milind B. Girkar, Sunnyvale, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "According to one example embodiment, there is disclosed herein uses partial recurrence relaxation for parallelizing DOACROSS loops on multi-core computer architectures. By one example definition, a DOACROSS may be a loop that allows successive iterations executing by overlapping; that is, all iterations must impose a partial execution order. According to one embodiment, the inventive subject matter may be used to transform the dependence structure of a given loop with recurrences for maximal degree of thread-level parallelism (TLP), where the threads can be mapped on to either different logical processors (in a hyperthreaded processor) or can be mapped onto different physical cores (or processors) in a multi-core processor." The patent application was filed on March 31, 2007 (11/695,012). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,431.PN.&OS=PN/79,84,431&RS=PN/79,84,431 Written by Rajat Puri; edited by Jaya Anand. *** California Inventor Develops Patent for Repository Relationship Programming ALEXANDRIA, Va., July 20 -- Kevin P. Graham, Brentwood, Calif., has developed a patent (7,984,422) for a repository relationship programming. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of systems, methods and computer program products are described for implementing repository relationship programming. Implementations described herein describe processes for implementing a union of concerns, integrating concerns, assembling concerns and separating concerns." The patent application was filed on Sept. 30, 2005 (11/239,849). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,422.PN.&OS=PN/79,84,422&RS=PN/79,84,422 Written by Rajat Puri; edited by Jaya Anand. *** NeXT Software Assigned Patent ALEXANDRIA, Va., July 20 -- NeXT Software, Redwood City, Calif., has been assigned a patent (7,984,451) developed by four co-inventors for a "method for associating data bearing objects with user interface objects." The co-inventors are Richard Williamson, San Francisco, Linus Upson, Half Moon Bay, Calif., Jack Greenfield, Reston, Va., and Dan Willhite, San Francisco. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention comprises a method for allowing a data controlling object to interface with any number of user interface objects without requiring separate interface code for each user interface object and without restricting the user interface to certain predetermined designs. The present method provides objects called association objects that are interposed between a data controlling object and each user interface object. Each kind of user interface object has a corresponding association object. The association object for a particular kind of user interface object contains code that allows the association object to interact with the specific kind of user interface object with which it is associated. Each association object also presents a standard interface to a data controlling object, regardless of the kind of user interface object with which the association object is associated. The association object takes care of any conversion or translation that must be performed to convert a data value sent by the data controlling object into an appropriate value that can be displayed by the user interface object. Accordingly, instead of requiring different interface code for each kind of user interface object used, a data controlling object requires only a single block of interface code for communicating with all association objects, which in turn provide the user interface specific code needed for each kind of user interface object." The patent application was filed on Sept. 28, 2004 (10/952,399). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,451&OS=79,84,451&RS=79,84,451 Written by Rajat Puri; edited by Jaya Anand. *** Hewlett-Packard Development Assigned Patent for Efficient Mechanism for Preventing Starvation in Counting Semaphores ALEXANDRIA, Va., July 20 -- Hewlett-Packard Development, Houston, has been assigned a patent (7,984,439) developed by Marcia E. McConnell, Los Altos Hills, Calif., for an "efficient mechanism for preventing starvation in counting semaphores." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An algorithm for preventing starving threads in a counting semaphore for a computer operating system. The algorithm operates in a stealing mode where threads can steal resources from other threads if none of the threads is starving, and operates in a first-in first-out mode if one or more of the threads becomes starving." The patent application was filed on March 8, 2005 (11/075,118). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,439&OS=79,84,439&RS=79,84,439 Written by Rajat Puri; edited by Jaya Anand. *** California Inventor Develops Patent for Intelligent Memory Device Multilevel ASCII Interpreter ALEXANDRIA, Va., July 20 -- Edwin E. Klingman, San Gregorio, Calif., has developed a patent (7,984,442) for an "intelligent memory device multilevel ASCII interpreter." The abstract of the patent published by the U.S. Patent and Trademark Office states: "System and method for interpreting ASCII code fetched from a code space of a task partition that is part of memory shared by a host processor For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1054852 (c) 2011 Targeted News Service |