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U.S. Patents Awarded to Inventors in Oregon (July 20)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., July 20 -- The following federal patents were awarded to inventors in Oregon. *** Intel Assigned Patent for Dynamic Updating of Thresholds in Accordance With Operating Conditions ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., has been assigned a patent (7,984,250) developed by five co-inventors for a "dynamic updating of thresholds in accordance with operating conditions." The co-inventors are Robin Steinbrecher, Olympia, Wash., Christian Le, North Plains, Ore., Rahul Khanna, Portland, Ore., Fernando A. Lopez, Hillsboro, Ore., and Kai Cheng, Portland, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "In some embodiments, a memory control device includes a sensor positioned remotely from a memory device, a register to store an offset value, the offset value corresponding to a difference between a temperature reading of the sensor and an estimated actual temperature of the memory device, and a controller to control an operation of the memory device, wherein the controller is configured to read the offset value from the register and control the operation of the memory device in accordance with the offset value. The controller may be configured to dynamically update the offset value during an operation of the memory device. Other embodiments are disclosed and claimed." The patent application was filed on Dec. 31, 2008 (12/317,965). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,250.PN.&OS=PN/79,84,250&RS=PN/79,84,250 Written by Ruby Maibam; edited by Jaya Anand. *** International Business Machines Assigned Patent for Systems for Providing Performance Monitoring in a Memory System ALEXANDRIA, Va., July 20 -- International Business Machines, Armonk, N.Y., has been assigned a patent (7,984,222) developed by Kevin C. Gower, LeGrangeville, N.Y., Carl E. Love, Beaverton, Ore., and Dustin J. VanStee, Poughkeepsie, N.Y., for "systems for providing performance monitoring in a memory system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation." The patent application was filed on Jan. 13, 2009 (12/352,990). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,222.PN.&OS=PN/79,84,222&RS=PN/79,84,222 Written by Ruby Maibam; edited by Jaya Anand. *** Null Networks Assigned Patent ALEXANDRIA, Va., July 20 -- Null Networks, Las Vegas, has been assigned a patent (7,984,457) developed by Jonathan A. Tuchow, Portland, Ore., for "software methods of an optical network apparatus with multiple multi-protocol optical networking modules having packet filtering resources." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An API is provided to an optical networking apparatus to facilitate uniform access, control and interaction with its multi-protocol optical networking modules (MPONM) by its applications. Each of the MPONM has a number of function blocks having corresponding drivers. In response to an application's request to initialize a MPONM, the initialization function of the API cooperates with the function block drivers to create a data structure for the MPONM, and returns a handle of the data structure to the application. Thereafter, in response to a need to have an operation performed in the packet filtering function block of a MPONM, the application makes the request to the API, including with the request the handle of the data structure of the MPONM. In response, the API allocates a packet filtering resource to perform the operation, and returns a handle corresponding to the allocated resource to the application for use in further requests. When the application is finished with the resource, the resource is de-allocated by the API." The patent application was filed on Oct. 2, 2008 (12/244,689). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,457&OS=79,84,457&RS=79,84,457 Written by Rajat Puri; edited by Jaya Anand. *** Cray Assigned Patent ALEXANDRIA, Va., July 20 -- Cray, Seattle, has been assigned a patent (7,984,453) developed by nine co-inventors for "event notifications relating to system failures in scalable systems." The co-inventors are Gail A. Alverson, Seattle, Robert L. Alverson, Seattle, Daniel C. Duval, Lincoln City, Ore., Eric A. Hoffman, Seattle, Laurence S. Kaplan, Seattle, Matthew Kelly, Eau Claire, Wis., Kazuya Okubo, Seattle, Mark Swan, Prescott, Wis., and Asaph Zemach, Seattle. The abstract of the patent published by the U.S. Patent and Trademark Office states: "An availability system is provided that includes a hierarchy of controllers for providing event notifications relating to availability of components of a scalable MPP system. A controller receives a subscription from a child controller that identifies an event type and a generator. The controller stores in a subscription store an indication that the subscription has been received from the child controller. When a parent controller has not yet been notified of a subscription with a matching event type and generator as indicated by the subscription store, the controller sends the subscription to the parent controller. When the parent controller has already been notified of a subscription with a matching event type and generator as indicated by the subscription store, the controller suppresses the sending of the subscription to the parent controller." The patent application was filed on Sept. 18, 2007 (11/857,261). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,453&OS=79,84,453&RS=79,84,453 Written by Rajat Puri; edited by Jaya Anand. *** Synopsys Assigned Patent for Techniques for use with Automated Circuit Design and Simulations ALEXANDRIA, Va., July 20 -- Synopsys, Mountain View, Calif., has been assigned a patent (7,984,400) developed by four co-inventors for "techniques for use with automated circuit design and simulations." The co-inventors are Richard C. Maixner, West Linn, Ore., Mario Larouche, Portland, Ore., Chun Kit Ng, Portland, Ore., and Kenneth S. McElvain, Menlo Park, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described." The patent application was filed on May 8, 2008 (12/117,705). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,400&OS=79,84,400&RS=79,84,400 Written by Rajat Puri; edited by Jaya Anand. *** Synopsys Assigned Patent for Method and Apparatus for Determining the Timing of an Integrated Circuit Design ALEXANDRIA, Va., July 20 -- Synopsys, Mountain View, Calif., has been assigned a patent (7,984,405) developed by Yiu-Chung Mang, Toronto, and Pei-Hsin Ho, Portland, Ore., for a "method and apparatus for determining the timing of an integrated circuit design." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system that determines the timing of an integrated circuit (IC) design is presented. During operation, the system receives a netlist for the IC design, wherein the netlist specifies the placement of cells within the IC design. Next, the system estimates capacitances for cells within the IC design based on analytic models of the cells. The system then estimates the post-physical-optimization timing of the IC design based on the netlist, the capacitances, and the analytic models, wherein the post-physical-optimization timing is estimated without performing physical optimization." The patent application was filed on Jan. 10, 2008 (11/972,521). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,405&OS=79,84,405&RS=79,84,405 Written by Rajat Puri; edited by Jaya Anand. *** Mentor Graphics Assigned Patent ALEXANDRIA, Va., July 20 -- Mentor Graphics, Wilsonville, Ore., has been assigned a patent (7,984,354) developed by four co-inventors for "generating responses to patterns stimulating an electronic circuit with timing exception paths." The co-inventors are Dhiraj Goswami, Wilsonville, Ore., Kun-Han Tsai, Lake Oswego, Ore., Mark Kassab, Wilsonville, Ore., and Janusz Rajski, West Linn, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression." The patent application was filed on June 29, 2009 (12/494,121). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,984,354.PN.&OS=PN/7,984,354&RS=PN/7,984,354 Written by Anjali Jha; edited by Jaya Anand. *** Intel Assigned Patent ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., has been assigned a patent (7,984,314) developed by Barnes Cooper, Tigard, Ore., Jaya L. Jeyaseelan, Cupertino, Calif., and Robert E. Gough, Cornelius, Ore., for a "power management of low power link states." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described." The patent application was filed on Sept. 29, 2007 (11/906,007). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,984,314.PN.&OS=PN/7,984,314&RS=PN/7,984,314 Written by Anjali Jha; edited by Jaya Anand. *** Intel Assigned Patent for Apparatus and Method for Secure Boot Environment ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., has been assigned a patent (7,984,286) developed by six co-inventors for an "apparatus and method for secure boot environment." The co-inventors are Vincent J. Zimmer, Federal Way, Wash., Mohan Kumar, Aloha, Ore., Mahesh Natu, Portland, Ore., Qin Long, Shanghai, China, Liang Cui, Shanghai, China, and Jiewen Yao, Shanghai, China. The abstract of the patent published by the U.S. Patent and Trademark Office states: "In some embodiments, a processor-based system may include at least one processor, at least one memory coupled to the at least one processor, a boot block stored at a first memory location, a capsule update stored at a second memory location, a startup authenticated code module to ensure the integrity of the boot block upon a restart of the processor-based system, code which is executable by the processor-based system to cause the processor-based system to validate the boot block with the startup authenticated code module upon the restart of the processor-based system, and, if the boot block is successfully validated, to validate the capsule update for the processor-based system with the startup authenticated code module. Other embodiments are disclosed and claimed." The patent application was filed on June 25, 2008 (12/215,071). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,984,286.PN.&OS=PN/7,984,286&RS=PN/7,984,286 Written by Anjali Jha; edited by Jaya Anand. *** J. Frank Schmidt & Son Assigned Patent ALEXANDRIA, Va., July 20 -- J. Frank Schmidt & Son, Boring, Ore., has been assigned a patent (PP22,034) developed by Keith S. Warren, Gresham, Ore., for a "sugar maple tree named 'JFS-KW8'." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A variety of sugar maple which combines unusually dark green summer foliage and bright red fall color with an upright branch orientation, straight trunk, and narrowly oval to oval canopy shape." The patent application was filed on April 2, 2010 (12/798,427). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=PP22,034&OS=PP22,034&RS=PP22,034 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Intel Assigned Patent for Address Window Support for Direct Memory Access Translation ALEXANDRIA, Va., July 20 -- Intel, Santa Clara, Calif., has been assigned a patent (7,984,203) developed by five co-inventors for an "address window support for direct memory access translation." The co-inventors are Rajesh Madukkarumukumana, Portland, Ore., Udo A. Steinburg, Sohland a.d. Spree, Germany, Steven M. Bennett, Hillsboro, Ore., Andrew V. Anderson, Hillsboro, Ore., and Gilbert Neiger, Portland, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "An apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit of the apparatus includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations." The patent application was filed on Dec. 29, 2009 (12/648,461). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7,984,203.PN.&OS=PN/7,984,203&RS=PN/7,984,203 Written by Shabnam Sheikh; edited by Jaya Anand. *** Hewlett-Packard Development Assigned Patent ALEXANDRIA, Va., July 20 -- Hewlett-Packard Development, Houston, has been assigned a patent (7,984,178) developed by seven co-inventors for a "synthetic bridging for networks." The co-inventors are Ted W. Beers, Corvallis, Ore., Mark E. Gorzynski, Corvallis, Ore., William C. Wickes, Corvallis, Ore., Jon A. Brewster, Monmouth, Ore., Garrett Daniel Gargan, Corvallis, Ore., Jeffrey L. Thielman, Corvallis, Ore., and Scott Grasley, Lebanon, Ore. The abstract of the patent published by the U.S. Patent and Trademark Office states: "An apparatus has a content node to logically select a first A/V stream from an application layer of a first network and a collaboration node to logically select a second A/V stream from an application layer of a second network. A set of non-network media link interfaces are configured to transmit the second A/V stream from the collaboration node to the content node, and to transmit the first A/V stream from content node to the collaboration node. The non-network media link interfaces provide for limited information encoding to prevent network protocol information from being transferred between the first and second networks." The patent application was filed on April 19, 2010 (12/762,927). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7,984,178.PN.&OS=PN/7,984,178&RS=PN/7,984,178 Written by Shabnam Sheikh; edited by Jaya Anand. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1054877 (c) 2011 Targeted News Service |