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U.S. Patents Awarded to Inventors in Vermont (July 20)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., July 20 -- The following federal patents were awarded to inventors in Vermont. *** International Business Machines Assigned Patent for Structures Incorporating Interconnect Structures with Improved Electromigration Resistance ALEXANDRIA, Va., July 20 -- International Business Machines, Armonk, N.Y., has been assigned a patent (7,984,409) developed by four co-inventors for "structures incorporating interconnect structures with improved electromigration resistance." The co-inventors are Louis Lu-Chen Hsu, Fishkill, N.Y., Jack Allan Mandelman, Flat Rock, N.C., William Robert Tonti, Essex Junction, Vt., and Chih-Chao Yang, Glenmont, N.Y. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening." The patent application was filed on Oct. 19, 2007 (11/875,193). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,409.PN.&OS=PN/79,84,409&RS=PN/79,84,409 Written by Rajat Puri; edited by Jaya Anand. *** International Business Machines Assigned Patent for Design Structure for a Redundant Micro-loop Structure ALEXANDRIA, Va., July 20 -- International Business Machines, Armonk, N.Y., has been assigned a patent (7,984,394) developed by six co-inventors for a "design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same." The co-inventors are Brent A. Anderson, Jericho, Vt., Jeanne P. Bickford, Essex Junction, Vt., Markus Buehler, Sindelfingen, Germany, Jason D. Hibbeler, Williston, Vt., Juergen Koehl, Weil im Schoenbuch, Germany, and Edward J. Nowak, Essex Junction, Vt. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via." The patent application was filed on Dec. 13, 2007 (11/955,580). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,394&OS=79,84,394&RS=79,84,394 Written by Rajat Puri; edited by Jaya Anand. *** Cadence Design Systems Assigned Patent ALEXANDRIA, Va., July 20 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (7,984,399) developed by four co-inventors for a "system and method for random defect yield simulation of chip with built-in redundancy." The co-inventors are Roland Ruehl, San Carlos, Calif., Mathew Koshy, San Mateo, Calif., Jonathan Fales, South Burlington, Vt., and Udayan Gumaste, San Jose, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture." The patent application was filed on Dec. 27, 2007 (11/965,681). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=79,84,399&OS=79,84,399&RS=79,84,399 Written by Rajat Puri; edited by Jaya Anand. *** International Business Machines Assigned Patent for System and Method for Providing Dram Device-level Repair via Address Remappings ALEXANDRIA, Va., July 20 -- International Business Machines, Armonk, N.Y., has been assigned a patent (7,984,329) developed by six co-inventors for a "system and method for providing DRAM device-level repair via address remappings external to the device." The co-inventors are Luis A. Lastras-Montano, Cortlandt Manor, N.Y., Darren L. Anand, Williston, Vt., Jeffrey H. Dreibelbis, Williston, Vt., Charles A. Kilmer, Essex Junction, Vt., Warren E. Maule, Cedar Park, Texas, and Robert B. Tremaine, Stormville, N.Y. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for providing DRAM device-level repair via address remappings external to the device. A system includes a memory controller having an interface to one or more memory devices via a memory module. The memory devices include addressable redundant and non-redundant memory blocks. The memory controller also includes a mechanism for utilizing one or more redundant memory blocks in place of one or more failing non-redundant memory blocks via an address remapping external to the memory device. The remapping occurs while the system is on-line." The patent application was filed on Sept. 4, 2007 (11/849,452). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,984,329.PN.&OS=PN/7,984,329&RS=PN/7,984,329 Written by Anjali Jha; edited by Jaya Anand. *** Gregson Assigned Patent ALEXANDRIA, Va., July 20 -- Abbie B. Gregson, Brownsville, Vt., has been assigned a patent (D641,653) developed by Abbie B. Gregson, Brownsville, Vt., and Ali R. Lotfi, Weston, Mass., for an ornamental design for a planter. The abstract of the patent published by the U.S. Patent and Trademark Office states: "The ornamental design for a planter, as is shown and described." The patent application was filed on Jan. 28, 2010 (D/354,760). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=D641,653.PN.&OS=PN/D641,653&RS=PN/D641,653 Written by Kusum Sangma; edited by Anand Kumar. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1054885 (c) 2011 Targeted News Service |