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U.S. Patents Awarded to Inventors in Idaho (July 4)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., July 4 -- The following federal patents were awarded to inventors in Idaho. *** Micron Technology Assigned Patent for Memory Array for Increased Bit Density and Method of Forming the Same ALEXANDRIA, Va., July 3 -- Micron Technology, Boise, Idaho, has been assigned a patent (7,968,927) developed by Jon Daley, Boise, Idaho, for a "memory array for increased bit density and method of forming the same." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element." The patent application was filed on March 15, 2010 (12/659,612). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,927.PN.&OS=PN/7,968,927&RS=PN/7,968,927 Written by Arpi Sharma; edited by Jaya Anand. *** Micron Technology Assigned Patent for Interconnecting Bit Lines in Memory Devices for Multiplexing ALEXANDRIA, Va., July 3 -- Micron Technology, Boise, Idaho, has been assigned a patent (7,968,951) developed by Seiichi Aritome, Boise, Idaho, for an "interconnecting bit lines in memory devices for multiplexing." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs." The patent application was filed on Sept. 15, 2009 (12/560,103). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,951.PN.&OS=PN/7,968,951&RS=PN/7,968,951 Written by Arpi Sharma; edited by Jaya Anand. *** Micron Technology Assigned Patent for Circuit and Method for Interconnecting Stacked Integrated Circuit Dies ALEXANDRIA, Va., July 3 -- Micron Technology, Boise, Idaho, has been assigned a patent (7,968,916) developed by Jacob Robert Anderson, Meridian, Idaho, and William Jones, Boise, Idaho, for a "circuit and method for interconnecting stacked integrated circuit dies." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively." The patent application was filed on Feb. 19, 2010 (12/709,261). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,916.PN.&OS=PN/7,968,916&RS=PN/7,968,916 Written by Arpi Sharma; edited by Jaya Anand. *** Micron Technology Assigned Patent for DRAM Layout with Vertical FETs and Method of Formation ALEXANDRIA, Va., July 3 -- Micron Technology, Boise, Idaho., has been assigned a patent (7,968,928) developed by Todd R. Abbott, Boise, Idaho, for a "DRAM layout with vertical FETs and method of formation." The abstract of the patent published by the U.S. Patent and Trademark Office states: "DRAM cell arrays having a cell area of less than about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is non-orthogonal to at least one of the vertical gate electrodes of the vertical transistors." The patent application was filed on March 21, 2008 (12/076,766). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,928.PN.&OS=PN/7,968,928&RS=PN/7,968,928 Written by Arpi Sharma; edited by Jaya Anand. *** Micron Technology Assigned Patent for Finned Memory Cells ALEXANDRIA, Va., July 3 -- Micron Technology, Boise, Idaho, has been assigned a patent (7,968,930) developed by Seiichi Aritome, Boise, Idaho, for a finned memory cells. The abstract of the patent published by the U.S. Patent and Trademark Office states: "For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching." The patent application was filed on Aug. 25, 2010 (12/868,389). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,930.PN.&OS=PN/7,968,930&RS=PN/7,968,930 Written by Arpi Sharma; edited by Jaya Anand. *** Micron Technology Assigned Patent ALEXANDRIA, Va., July 3 -- Micron Technology, Boise, Idaho, has been assigned a patent (7,968,954) developed by Zhongze Wang, Boise, Idaho, for an "intermediate semiconductor device having nitrogen concentration profile." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion." The patent application was filed on June 1, 2007 (11/756,922). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,954.PN.&OS=PN/7,968,954&RS=PN/7,968,954 Written by Arpi Sharma; edited by Jaya Anand. *** Micron Technology Assigned Patent for Phase Change Memory Elements Using Self-aligned Phase Change Material Layers ALEXANDRIA, Va., July 4 -- Micron Technology, Boise, Idaho, has been assigned a patent (7,968,862) developed by Jun Liu, Boise, Idaho, for a "phase change memory elements using self-aligned phase change material layers." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A phase change memory element and method of forming the same. The memory element includes a substrate supporting a first electrode. An insulating material element is positioned over the first electrode, and a phase change material layer is formed over the first electrode and surrounding the insulating material element such that the phase change material layer has a lower surface that is in electrical communication with the first electrode. The memory element also has a second electrode in electrical communication with an upper surface of the phase change material layer." The patent application was filed on March 9, 2009 (12/400,044). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,862.PN.&OS=PN/7,968,862&RS=PN/7,968,862 Written by Arpi Sharma; edited by Jaya Anand. *** Aptina Imaging Assigned Patent ALEXANDRIA, Va., July 4 -- Aptina Imaging, Grand Cayman, Ky., has been assigned a patent (7,968,042) developed by Rickie C. Lake, Meridian, Idaho, for a "method and apparatus for step-and-repeat molding." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for molding a structure on the top surface of a substrate. Mold material is dispensed onto an area of the top surface of the substrate. The mold apparatus is positioned over the area. The mold portion of the mold apparatus is positioned above the mold material and the mold material is surrounded with a shroud of the mold apparatus. A seal is formed between the shroud and the top surface of the substrate. The pressure is reduced within the shroud to below the ambient pressure. The mold portion of the mold apparatus is lowered toward the top surface of the substrate, so that at least the outer edge of the mold portion is in contact with the mold material. The pressure within the shroud is raised to at least the ambient pressure, and the mold material is cured to form the structure." The patent application was filed on April 16, 2008 (12/103,816). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7968042.PN.&OS=PN/7968042&RS=PN/7968042 Written by Kusum Sangma; edited by Anand Kumar. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1053181 (c) 2011 Targeted News Service |