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U.S. Patents Awarded to Inventors in Oregon (July 4)
[July 04, 2011]

U.S. Patents Awarded to Inventors in Oregon (July 4)


(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., July 4 -- The following federal patents were awarded to inventors in Oregon.

*** Intel Assigned Patent for Stressed Barrier Plug Slot Contact Structure for Transistor Performance Enhancement ALEXANDRIA, Va., July 3 -- Intel, Santa Clara, Calif., has been assigned a patent (7,968,952) developed by Kevin J. Fischer, Hillsboro, Ore., Vinay B. Chikarmane, Portland, Ore., and Brennan L. Peterson, Portland, Ore., for a "stressed barrier plug slot contact structure for transistor performance enhancement." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an embodiment, a stress inducing barrier plug is disposed within a portion of the contact opening and the remainder of the contact opening is filled with a lower resistivity contact metal. By selecting the proper materials and deposition parameters, the slot contact can be tuned to induce a tensile or compressive stress on the adjacent channel region, thus being applicable for both p-type and n-type devices." The patent application was filed on Dec. 29, 2006 (11/648,098). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,952.PN.&OS=PN/7,968,952&RS=PN/7,968,952 Written by Arpi Sharma; edited by Jaya Anand.

*** Intel Assigned Patent ALEXANDRIA, Va., July 3 -- Intel, Santa Clara, Calif., has been assigned a patent (7,968,957) developed by seven co-inventors for a "transistor gate electrode having conductor material layer." The co-inventors are Anand Murthy, Portland, Ore., Boyan Boyanov, Portland, Ore., Suman Datta, Beaverton, Ore., Brian S. Doyle, Portland, Ore., Been-Yih Jin, Beaverton, Ore., Shaofeng Yu, Plano, Texas, and Robert Chau, Beaverton, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material." The patent application was filed on Sept. 29, 2010 (12/893,983). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,957.PN.&OS=PN/7,968,957&RS=PN/7,968,957 Written by Arpi Sharma; edited by Jaya Anand.


*** LSI Assigned Patent ALEXANDRIA, Va., July 4 -- LSI, Milpitas, Calif., has been assigned a patent (7,968,859) developed by Roger Y.B. Young, Vancouver, Wash., John A. Knoch, Portland, Ore., and Jason W. McNichols, Portland, Ore., for a "wafer edge defect inspection using captured image analysis." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A wafer edge defect inspection method and apparatus for use in an integrated circuit fabrication system includes an image capturing device for capturing images of the edges of wafers, a database in which the images are stored and accessible for analysis and a computer for analyzing the images of one or more wafer edges to locate edge defects and for evaluating the performance of the fabrication system. The inspection and data storage are performed automatically. The database storage enables detailed analysis of many wafers and fabrication process steps." The patent application was filed on July 28, 2003 (10/628,614). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,859.PN.&OS=PN/7,968,859&RS=PN/7,968,859 Written by Arpi Sharma; edited by Jaya Anand.

*** Xerox Assigned Patent ALEXANDRIA, Va., July 4 -- Xerox, Norwalk, Conn., has been assigned a patent (7,967,902) developed by five co-inventors for "compounds suitable for use in inks and inks having such compounds." The co-inventors are Jeffrey H. Banning, Hillsboro, Ore., Stephan V. Drappel, Mississauga, Canada, Michael B. Meinhardt, Lake Oswego, Ore., Randall R. Bridgeman, Tualatin, Ore., and Alex J. Kugel, Fargo, N.D.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Disclosed herein are compounds having a formula of: R.sup.1--CONH--R.sup.6--CONH--C.sub.34H.sub.64+n--CONH--R.sup.6--CONH--R.- sup.3, R.sup.1--NHCO--R.sup.6--NHCO--C.sub.34H.sub.64+n--NHCO--R.sup.6--NH- CO--R.sup.3, R.sup.1--CONH--R.sup.6--NHCO--C.sub.34H.sub.64+n--CONH--R.sup.6--NHCO--R.- sup.3, R.sup.1--NHCO--R.sup.6--CONH--C.sub.34H.sub.64+n--NHCO--R.sup.6--CO- NH--R.sup.3, R.sup.1--CONH--R.sup.4--CONH--C.sub.34H.sub.64+n--CONH--R.sup.5--CONH--R.- sup.3, R.sup.1--CONH--R.sup.4--NHCO--C.sub.34H.sub.64+n--CONH--R.sup.5--NH- CO--R.sup.3, R.sup.1--NHCO--R.sup.4--CONH--C.sub.34H.sub.64+n--NHCO--R.sup.5--CONH--R.- sup.3, R.sup.1--NHCO--R.sup.4--NHCO--C.sub.34H.sub.64+n--CONH--R.sup.5--CO- NH--R.sup.3, or R.sup.1--CONH--R.sup.4--CONH--C.sub.34H.sub.64+n--NHCO--R.sup.5--NHCO--R.- sup.3, wherein n is an integer of 0, 2 or 4, R.sup.6 is the same or different cyclic group having from 5 to 8 carbon atoms, R.sup.4 and R.sup.5 are the same or different and comprise an alkylene having from 1 to about 200 carbon atoms, and R.sup.1 and R.sup.3 are the same or different and comprise a straight chain or branched alkyl group having from about 3 carbon atoms to about 200 carbon atoms and one or both of R.sup.1 and R.sup.3 include at least one hydroxyl group substituent, and ink compositions including the compounds as an ink vehicle." The patent application was filed on Nov. 17, 2010 (12/948,551). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,967,902.PN.&OS=PN/7,967,902&RS=PN/7,967,902 Written by Arpi Sharma; edited by Jaya Anand.

*** Hewlett-Packard Development Assigned Patent for Optical Recording System ALEXANDRIA, Va., July 4 -- Hewlett-Packard Development, Houston, has been assigned a patent (7,968,166) developed by Makarand P. Gore, Corvallis, Ore., for an optical recording system.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and method for optically recording data. One system comprises a disc comprising a substrate and a markable coating on said substrate, the markable coating having a thickness less than 1 .mu.m and comprising: a matrix; and a color-forming agent included in the matrix and comprising a leuco dye and developer; wherein the leuco dye is selected to change from high reflectance of radiation with wavelengths between 400 and 500 nm to low reflectance of radiation with wavelengths between 400 and 500 nm when activated by the application of energy above a threshold level; and a marking light source positioned so as to illuminate the disc in a desired manner." The patent application was filed on Jan. 29, 2007 (11/668,438). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,968,166&OS=7,968,166&RS=7,968,166 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Xerox Assigned Patent ALEXANDRIA, Va., July 4 -- Xerox, Norwalk, Conn., has been assigned a patent (7,968,035) developed by five co-inventors for a "forged ink stick fabrication from in-line extrusion." The co-inventors are Brent Rodney Jones, Sherwood, Ore., Frederick T. Mattern, Portland, Ore., Gustavo J. Yusem, Tigard, Ore., Edward F. Burress, West Linn, Ore., and Dan Leo Massopust, Powell Butte, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of manufacturing an ink stick for use in a phase change ink jet imaging device comprises heating phase change ink material to an extrusion temperature at which the phase change ink material is in a malleable state. The heated ink material is then extruded through an extrusion orifice to form an extruded element. A forging element is then pressed against the extruded element to form an ink stick." The patent application was filed on Oct. 11, 2006 (11/546,102). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7968035.PN.&OS=PN/7968035&RS=PN/7968035 Written by Kusum Sangma; edited by Anand Kumar.

*** Novellus Systems Assigned Patent ALEXANDRIA, Va., July 4 -- Novellus Systems, San Jose, Calif., has been assigned a patent (7,967,969) developed by Steven T. Mayer, Lake Oswego, Ore., and Jonathan D. Reid, Sherwood, Ore., for a "method of electroplating using a high resistance ionic current source." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A substantially uniform layer of a metal is electroplated onto a work piece having a seed layer thereon. This is accomplished by employing a "high resistance ionic current source," which solves the terminal problem by placing a highly resistive membrane (e.g., a microporous ceramic or fretted glass element) in close proximity to the wafer, thereby swamping the system's resistance. The membrane thereby approximates a constant current source. By keeping the wafer close to the membrane surface, the ionic resistance from the top of the membrane to the surface is much less than the ionic path resistance to the wafer edge, substantially compensating for the sheet resistance in the thin metal film and directing additional current over the center and middle of the wafer." The patent application was filed on Oct. 13, 2009 (12/578,310). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7967969.PN.&OS=PN/7967969&RS=PN/7967969 Written by Kusum Sangma; edited by Anand Kumar.

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