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U.S. Patents Awarded to Inventors in Vermont (June 16)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., June 16 -- The following federal patents were awarded to inventors in Vermont. *** International Business Machines Assigned Patent for Design Structure for Compensating for Variances of a Buried Resistor in an Integrated Circuit ALEXANDRIA, Va., June 16 -- International Business Machines, Armonk, N.Y., has been assigned a patent (7,962,322) developed by Elie Awad, Essex Junction, Vt., Mariette Awad, Essex Junction, Vt., and Kai Di Feng, Hopewell Junction, N.Y., for a "design structure for compensating for variances of a buried resistor in an integrated circuit." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a circuit that compensates for variances in the resistance of the buried resistor during operation of the integrated circuit using a waveform that is representative of the thermal characteristics of the buried resistor." The patent application was filed on June 9, 2008 (12/135,232). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,962,322.PN.&OS=PN/7,962,322&RS=PN/7,962,322 Written by Arpi Sharma; edited by Jaya Anand. *** International Business Machines Assigned Patent ALEXANDRIA, Va., June 16 -- International Business Machines, Armonk, N.Y., has been assigned a patent (7,962,508) developed by four co-inventors for a "system and method for searching and retrieving related messages." The co-inventors are Paul B. Moody, Hyde Park, Vt., Daniel M. Gruen, Newton, Mass., Steven L. Rohall, Winchester, Mass., and Bernard J. Kerr, Boston. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method is provided which utilizes a threading service to offer enhanced features for a document management system including an email system. Various enhanced email features may be provided through one or more of the following components: a delete module, a reply module, a profile module, and a search module. The delete module enables a user to delete a selected message, a set of related messages, or the whole set except for the selected message. The reply module enables a user to send a reply message to all addresses associated and involved with an entire set of related messages. The profile module enables a dynamic interest profile to contain all relevant information from an outgoing message and a set of messages related to the outgoing message. The search module enables search results to include documents which match the user's query as well as documents related to the documents which match the user's query." The patent application was filed on May 16, 2008 (12/122,554). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7962508.PN.&OS=PN/7962508&RS=PN/7962508 Written by Kusum Sangma; edited by Anand Kumar. *** International Business Machines Assigned Patent for Method and System for Integrating SRAM and DRAM Architecture in Set Associative Cache ALEXANDRIA, Va., June 16 -- International Business Machines, Armonk, N.Y., has been assigned a patent (7,962,695) developed by six co-inventors for a "method and system for integrating SRAM and DRAM architecture in set associative cache." The co-inventors are Marc R. Faucher, South Burlington, Vt., Hillery C. Hunter, Somers, N.Y., William R. Reohr, Ridgefield, Conn., Peter A. Sandon, Essex Junction, Vt., Vijayalakshmi Srinivasan, New York, and Arnold S. Tran, South Burlington, Vt. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of integrating a hybrid architecture in a set associative cache having a first type of memory structure for one or more ways in each congruence class, and a second type of memory structure for the remaining ways of the congruence class, includes determining whether a memory access request results in a cache hit or a cache miss; in the event of a cache miss, determining whether LRU way of the first type memory structure is also the LRU way of the entire congruence class, and if not, then copying the contents of the LRU way of the first type memory structure into the LRU way of the entire congruence class, and filling the LRU way of the first type memory structure with a new cache line in the event of a cache miss; and updating LRU bits, depending upon the results of the memory access request." The patent application was filed on Dec. 4, 2007 (11/949,935). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=7,962,695&OS=7,962,695&RS=7,962,695 Written by Satyaban Rath; edited by Hemanta Panigrahi. For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1051337 (c) 2011 Targeted News Service |