[March 18, 2011] NetLogic Microsystems Releases Line of Offerings to Lower Latency for Data Centers Tweet Mar 18, 2011 (Close-Up Media via COMTEX) -- NetLogic Microsystems, a provider of intelligent semiconductor solutions for Internet networks, announced the introduction of new offerings in high-speed physical layer SerDes development that has resulted in the world's lowest latency 10 Gigabit Ethernet (GbE) PHY solution for data centers. With the strong growth in cloud computing, large data centers, high-frequency financial trading, online advertisement insertion and high-performance computing, the response time or latency of the network becomes one of the most critical elements in data center performance. These applications require lower latency to improve user experience and financial profits. Every nanosecond of latency in the data center, for example, can make a difference in price points on a large trading exchange in the financial industry. NetLogic Microsystems' new dual-channel AEL2020-LL PHY with integrated SerDes features an ultra low-latency of 70 nanoseconds (ns), which is nearly a half of existing solutions. In addition to the ultra low-latency, the AEL2020-LL PHY device offers the industry's lowest power consumption and supports multiple protocols and multiple media types - single-mode fiber (10GBASE-LR), multi-mode fiber (10GBASE-SR and 10GBASE-LRM), direct-attached copper (10GBASE-CR) and extended reach optics (10GBASE-ER). "As a provider of ultra-low latency 10 Gigabit Ethernet switches for clouds and data centers, we are very pleased with NetLogic Microsystems' continued technical leadership in reducing PHY latency," said Andy Bechtolsheim, chairman and chief development officer at Arista Networks. "Our close collaboration with NetLogic Microsystems has been key to achieve the lowest Ethernet switch latency in the industry." "We are pleased to have once again raised the bar for the industry by delivering our 10GbE PHY products with the best latency, power and jitter performance to effectively address data center requirements," said Stefanos Sidiropoulos, VP of Physical Layer Products at NetLogic Microsystems. "By continually pushing the envelope on product developments and process technology, we are able to stay ahead of our competition and grow our share in the market." The AEL2020-LL dual-channel PHY device provides full Physical Coding Sublayer (PCS), PMA, and XGXS sub-layer functionality through the consolidation of the receiver and transmitter PHY functions on a single chip along with the integration of encode/decode/alignment logic, FIFOs, on-chip clock generation and data recovery, multiple loop-back features, PRBS Ethernet frame generation and verification for both the line- and the system-side. The AEL2020-LL device also features Packet, Pseudo Random Binary Sequence (PRBS), CJPAT and CRPAT generators and checkers; Management Data Input/Output (MDIO), Joint Test Action Group (JTAG), SDA/SCL physical interfaces, and is available in RoHS 5/6 and RoHS 6/6 package options. ((Comments on this story may be sent to [email protected])) [ Back To TMCnet.com's Homepage ]