[September 23, 2009] Achronix Introduces 120 Gbps Reprogrammable Networking System Tweet Sep 22, 2009 (Close-Up Media via COMTEX) -- Achronix Semiconductor, makers of field-programmable gate arrays (FPGAs), announced the availability of Bridge100, a 120 Gbps Infiniband-to-Ethernet programmable platform. Achronix stated that the fully reprogrammable Bridge100 provides an array of 1.5 GHz Achronix SPD60 FPGAs, 8 GB of additional on-board memory (upgradeable to 32GB), and two 120 Gbps communication ports that give the user access to the full performance, memory, bandwidth, capacity, and flexibility required in today's high-performance networking applications. The company explained that the Achronix Bridge100 Platform introduction comes as the enterprise network evolves to better manage the convergence of voice, video and data. Supporting these traffic types requires increased attention to quality of service (QoS) -- handling traffic streams according to their specific needs rather than in a monolithic best-effort manner. At the same time, system designers are looking at FPGAs as a way to speed time-to-market and cut development costs in a competitive global environment. "Instead of merely claiming to support 100G applications, we have built a system enabling 100G interface between networks of different protocol," said Yousef Khalilollahi, Achronix worldwide vice president of sales and marketing. "Our Bridge100 Platform serves as a connection between different protocols, including Infiniband and Ethernet, to maximize total system performance." The Achronix Bridge100 platform offers two 120 Gbps bidirectional interfaces: three QSFP connectors on one side, and 12 XFP connectors on the other. All Speedster high-performance FPGA features are available, including logic, RAMs, multipliers, SerDes, programmable I/Os and the Achronix patented picoPIPE acceleration technology. The programmable logic takes the form of an array of SPD60s from the Achronix Speedster family of FPGAs -- the world's fastest reprogrammable logic devices, with up to 1.5GHz in fabric performance. The high datapath bandwidth of each SPD60 (10.3 Gbps SerDes) provides more than enough bandwidth to support two 100 Gbps interfaces (Ethernet, Infiniband). Additional SerDes lanes are used in 60 Gbps chip-to-chip links, effectively fusing the SPD60s into one "megachip." Each SPD60 provides up to 273 Gbps of raw DDR3 memory bandwidth. The Bridge100 comes loaded with eight DDR3 modules, a QDRII+ memory, and a NetLogic Search Engine (CAM). This memory is in addition to the 3.3 Mb per SPD60 (30 Mb total) embedded in the FPGA devices. These ample memory resources are available for packet buffering, classification, scheduling and traffic shaping, and statistics gathering. The features of the Speedster family (logic performance, SerDes and DDR3 bandwidth), are the foundation for the Bridge100, a fully reprogrammable 120 Gbps networking platform. ((Comments on this story may be sent to [email protected])) [ Back To TMCnet.com's Homepage ]