[November 21, 2008] NEC Electronics Selects Mentor Graphics Calibre nmLVS for Circuit Characterization at 40nm and Below Tweet Nov 22, 2008 (10Meters.com via COMTEX) -- Mentor Graphics Corp. announced that NEC Electronics Corp. has selected the Calibre nmLVS product to establish a circuit characterization flow for 40nm and below. The Calibre nmLVS verification tool includes features such as device parameter (ADP) extraction to enable customer-specific circuit characterization, as well as interactive debugging capabilities. "Mentor's Calibre nmLVS product with the ADP extraction feature enables us to extract highly-accurate circuit characteristics better reflecting our industry-leading semiconductor processes by taking into account systematic variation of layout context among the transistors themselves, and within the surrounding region," said Haruji Futami, Senior Manager, Core Development Division, Technology Foundation Development Operations Unit. "This capability allows NEC Electronics to ensure more accurately designed LSI without any additional changes to our existing design flow. For this reason we are incorporating Calibre nmLVS into our standard design flow for high-density, high-performance LSI development, starting with products implemented at 40nm and below." NEC Electronics uses the Calibre nmLVS solution in a design flow that estimates the systematic variation in electric characteristics caused by differences in the way layout shapes are implemented on the wafer, which is a growing concern at smaller process geometries. The Calibre nmLVS tool extracts circuit values taking into consideration interactions among adjacent gates, and stress effects introduced by shallow trench isolation (STI). By using a script developed by NEC Electronics, extracted geometric data is fed into NEC Electronics' proprietary gate pitch dependent characteristics variation model, and an STI stress induced characteristics variation model, which was developed by the MIRAI project lead by Selete under contract to NEDO (New Energy and Industrial Technology Development Organization). "Meeting the needs of our customers working at leading edge process nodes requires us to evolve our tools at every step of the IC implementation flow," said Joseph Sawicki, VP and general manager for the design-to-silicon division at Mentor Graphics. "Because our solutions are all based on a common Calibre nm Platform, we can provide functional and performance advancements in a timely and consistent manner, enabling our customers to create highly flexible and well-integrated flows." The Calibre nmLVS solution provides capabilities including multithreading and distributed computing performance improvements to enable LVS comparisons in minutes, even for the largest designs at 45nm and below. ADP extraction provides built-in device recognition and parameter extraction for standard devices with typical BSIM3/4 and PSP parameters, as well as user-defined parameters defined with SVRF and Tcl rules to enable extraction tailored to the customer's manufacturing process and the layout design rules. ((Comments on this story may be sent to [email protected])) ((Distributed via M2 Communications Ltd - http://www.m2.com)) http://www.10meters.com Comments on this story may be sent to [email protected] [ Back To TMCnet.com's Homepage ]