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$6M EU project investigating architectures for networks-on-chip
(Electronic Engineering Times Via Acquire Media NewsEdge) LONDON - Europe is mounting a collaborative research project to develop a design process for globally asynchronous, locally synchronous (GALS) architecture chips, together with novel network-on-chip (NoC) capabilities.
Arteris Inc., originally a French company, operates commercially in this area. It recently relocated its headquarters to San Jose, Calif.
Project Galaxy (GALS Interface for Complex Digital System Integration), which kicked off in June, has funding of 4 million euros (about $6.4 million) under the European Union's Seventh Framework Program (2007-2013). It is being carried out by a consortium led by research institute IHP GmbH (Frankfurt-Oder, Germany).
The project aims to evaluate the ability of the low-power GALS approach to solve system integration issues. The results will be demonstrated by implementing a complex wireless communication system.
Increased complexity and performance requirements and the need to reduce power and electromagnetic interference (EMI) are heady challenges for designers of complex chips, and the push toward nanoscale dimensions brings additional challenges for embedded-system design. A GALS methodology is seen as one promising option to deal with these issues.
Most of the today's designs are synchronous; that is, there is a common clock signal driving all blocks in the design. It is possible, however, for system blocks to operate synchronously internally but to communicate asynchronously. In this case, there is no need for a common clock that synchronizes all blocks. Such a scheme is usually referred to as a GALS system.
The Galaxy project's goal is to promote GALS system design by providing an interoperability framework for existing open or commercial CAD tools. Participants will explore and evaluate the ability of GALS to solve integration issues while building on its reduced-EMI and low-power properties.
A promising target platform is network-on-chip (NoC) design. In this project, different approaches for implementing GALS-enabled NoC platforms will be investigated and compared with fully synchronous implementations.
European taxpayers will foot nearly three-quarters of the bill for the project through the European Commission. The rest comes from project partners, including the Universities of Manchester, England, and Bologna, Italy, along with Ecole Polytechnique Federale (Lausanne, Switzerland), Silistix Ltd. (Manchester) and Infineon Technologies AG (Munich, Germany).
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