[July 03, 2008] Altera Introduces New Version of DSP Builder Tool Tweet (Wireless News Via Acquire Media NewsEdge) Altera has announced its DSP Builder tool version 8.0, featuring second-generation model-based synthesis technology. According to company officials, the technology allows DSP designers to automatically generate timing-optimized RTL code based on high-level Simulink design descriptions. "DSP Builder's second-generation model-based synthesis technology allows customers to use Simulink as the modeling, simulation and implementation environment of choice for high-performance DSP designs," said Ken Karnofsky, marketing director for signal processing and communications at The MathWorks. "This technology allows designers to vastly improve their productivity as they implement DSP functionality on Altera's FPGAs." Altera also said that the DSP Builder tool automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital pre distortion (DPD). "Altera continues to set the standard for FPGA design productivity, including high-performance DSP designs," said Chris Balough, marketing director for software, embedded, and DSP at Altera. "The innovative synthesis technology included in DSP Builder version 8.0 delivers a timing-driven FPGA implementation environment that allows designers to get the system performance they require with the push of a button--enabling an order-of-magnitude productivity gain." Altera creates programmable solutions for system and semiconductor companies. ((Comments on this story may be sent to [email protected])) ((Distributed on behalf of 10Meters via M2 Communications Ltd - http://www.m2.com)) ((10Meters - http://www.10meters.com)) Copyright ? 2008 Wireless News [ Back To TMCnet.com's Homepage ]