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Chipworks Discovers IBM Strain at 90nm, Delay in Low-k OTTAWA --(Business Wire)-- Sept. 8, 2004 -- Chipworks Inc. ("Chipworks") today disclose findings from their analysis of the IBM PPC970FX6SB chip found inside an Apple Xserve G5 server. This is the second 90nm device Chipworks has analyzed that does not use low-k dielectric, but follows the trend set by Intel using strained silicon.At the IEEE Solid-State Circuits Conference (ISSCC) in February 2004, IBM announced the migration of their 130nm PowerPC 970 to 90nm, reduced die size by almost 50%, and significant reductions in power consumption. The paper described the 90nm process as strained CMOS with silicon-on-insulator (SOI), with a minimum gate length of 46nm, three (3) gate dielectric thicknesses between 1-2nm, and an SRAM cell size of 1.06 microns m2. It also detailed 10 levels of metal with fluorine-doped TEOS (FTEOS) dielectric, a form of fluoro-silicate glass (FSG), in the back-end process. "These process and architecture innovations enable significant cost and power reductions", remarked Chipworks' president, Julia Elvidge. "The PowerTune scaling, together with the SOI, allows operation as low as 15 W." Chipworks' analysis confirms a minimum NMOS gate length of 45nm, and PMOS gate length of 60nm. The SRAM Tox is 1.5nm, with a cell size of 1.1 microns m2. There are ten layers of copper metallization, with an aluminum bond pad layer and a tungsten local interconnect/contact layer. The SOI body thickness is 45nm on a 150nm buried oxide layer, and source/drain and gates are cobalt silicided. "Once again IBM has come forward with a leading-edge process, the first to integrate strained silicon and SOI, and impressively small transistors", stated Dick James, Chipworks' senior technology analyst. "Our analysis shows that the NMOS transistors use nitride strain, similar to the Intel Prescott, but there does not appear to be any PMOS strain." Press commentary at the time of ISSCC indicated that IBM may be using a technique they called Strained Silicon Directly on Insulator (SSDOI), in which a Silicon-Germanium (SiGe) layer is used to strain the SOI layer, and then removed, leaving a strained silicon layer on the buried oxide. This technique strains the NMOS and PMOS transistors simultaneously. "We have done electron-beam diffraction with our transmission electron microscope (TEM) on the SOI, to look at the crystal structure, but we could not see any lattice distortion. IBM's SSDOI paper indicated that more than 1% tensile strain is needed to enhance hole mobility, and we think that this should be visible with TEM analysis", commented James. "The SSDOI work was presented at last December's International Electron Devices Meeting (IEDM), so it is not surprising that such advanced research has not made it into production yet. It will be interesting to compare the 970FX with AMD's 90nm SOI part, which is currently under analysis in our labs." Even though the ISSCC paper detailed FTEOS in the back-end, Chipworks was surprised to find FSG as the inter-metal dielectric, since IBM's foundry publicity includes low-k dielectric. Press reports have rumored that IBM has chosen Applied Materials' (AMAT) equipment to develop their own SiCOH low-k film, rather than AMAT's Black Diamond process. "IBM has been conservative with the 970FX, and used almost the same dielectric stack as in their 130nm back-end", said James. "The dielectric matrix is a bi-layer, with an FSG inter-metal layer, with oxide at the via levels, and oxynitride cap layers on the upper metal levels. There are no etch-stop layers for the metal trenches, but historically IBM have not used them. They have changed the cap layers on the lowest four copper levels to SiOCN to reduce the effective dielectric constant a little." "They have been reported to be qualifying low-k during the last few months, and we are expecting to see low-k product soon. We want to compare it with the other low-k processes that we have analyzed." Mr. James presented a detailed review of low-k structures at SEMICON West in July. "We looked at three low-k materials, AMAT's Black Diamond, Novellus' Coral, and ASM's Aurora, as well as the different implementations by AMD, TSMC, Sony, TI, and Intel. We found it fascinating that the detailed structure of each application was different - good confirmation of the difficulty of integrating these low-k materials. If low-k is not needed for the Apple's performance specifications, it is sensible for IBM to stick with FSG", commented James. Copies of the paper are available from Chipworks on request. Chipworks' analysis results of the PPC970FX and other 90nm technology innovations are available in ready-to-buy structural analysis reports. They assist process engineers in examining examine different approaches to nanometer silicon. Reports include an overview, package and die photos, process, transistor, materials and dielectric analyses, as well as critical die dimensions. About Chipworks Chipworks is an internationally recognized technical services company that analyzes the circuitry and physical composition of semiconductor chips and electronics systems for applications in patent licensing support and competitive study. Chipworks' technical experts use sophisticated lab facilities and a rich library of in-house semiconductor data and expertise to conduct detailed analyses of a wide selection of chip types. Chipworks develops high value, meticulously researched, on-time reports presented in a format that is easy to understand and tailored to customer needs. For over 12 years, Chipworks has successfully helped semiconductor and electronics organizations achieve their goals by supporting research and development efforts and patent portfolio management. Headquartered in Ottawa, Canada, the Company has offices worldwide. Chipworks can be visited via the Internet at www.chipworks.com. |
