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Lattice Updates Software Design Tools for Hot Swap Control and Power Management
(Market Wire Via Acquire Media NewsEdge) HILLSBORO, OR -- (MARKET WIRE) -- 11/09/09 --
Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 5.2 of its PAC-Designer® mixed signal
design tool suite with new device support and productivity features. The
PAC-Designer 5.2 software now supports two new higher performance Power
Manager II products: the ispPAC®-POWR1014-2 and ispPAC-POWR1014A-2
devices. The POWR1014/A-2 devices are ideal for integrating Hot Swap
control, voltage rail supervision and power supply sequencing ICs.
PAC-Designer 5.2 software also supports an expanded input operating
frequency range of 40-400MHz for ispClock(TM)5400D devices and a new
graphical editor for phase and time skew programming.
Lattice Power Manager II devices integrate programmable analog and PLD
technologies to support digital power management solutions. As more
digital management functions are integrated, the verification step in the
design flow depends on robust simulation technology. The PAC-Designer 5.2
software provides a new VHDL or Verilog HDL export feature to extract
simulation models of the embedded PLD block featured on all Lattice Power
Manager II family devices. This allows for functional verification of
sequence and supervisory logic by the Aldec Active-HDL Lattice Web Edition
simulator.
"By adding Active-HDL to the PAC-Designer software verification flow,
Lattice has provided a high-quality simulation and verification solution
for their power management product line. Logic targeted to the PLD block
of a Lattice Power Manager II family device can now be simulated with
Aldec's IEEE standard VHDL/Verilog single or mixed language simulators,"
said Dave Rinehart, Vice President of Marketing, Aldec, Inc. "As an
extension to our current OEM agreement, all Aldec simulation products,
including the Active-HDL Lattice Web Edition, now include support for the
Lattice Power Manager II family at no cost to Lattice customers."
Power Manager II devices are commonly used to integrate discrete ICs for
power management such as voltage supervisors, reset generators, watchdog
timers and Hot Swap controllers. By adding HDL export features to
PAC-Designer software, power supply sequencing, reset signal distribution,
and other digital logic integrated into a Power Manager II device can be
modeled with IEEE industry standard Verilog HDL or VHDL. PAC-Designer and
Active-HDL Lattice Web Edition software can be downloaded for free from:
www.latticesemi.com/products/designsoftware/pacdesigner
"PAC-Designer software remains an important reason why engineers continue
to adopt Lattice power management and programmable clock devices. Our
design environment is very easy to use and it offers both analog and
digital specialists the ability to complete designs quickly and
confidently," said Chris Fanning, Lattice Corporate Vice President and
General Manager of Low Density and Mixed Signal Solutions. "PAC-Designer
5.2 software supports the expanded performance of the POWR1014/A-2 and
ispClock 5400D devices, which lowers cost and provides more hardware
flexibility. The PAC-Designer interface to Active-HDL allows designers to
use one of the market's most effective EDA tools for HDL simulation."
Productivity Features
The PAC-Designer 5.2 software includes an upgrade to the LogiBuilder
component, which can now export VHDL or Verilog HDL simulation models of
the embedded PLD block of a Power Manager II device. This allows
functional verification of sequence and supervisory logic in any popular
EDA simulator, including the Aldec Active-HDL Lattice Web Edition
simulator.
PAC-Designer 5.2 software also supports printing of sequence logic
equations directly from the LogiBuilder window.
The PAC-Designer software environment makes programmable clock design entry
and verification easy, with a graphical block diagram editor for reference
clock settings, feedback control and time/phase skew management.
PAC-Designer 5.2 software now also provides a graphical skew editor for
ispClock 5400D devices.
About the Lattice PAC-Designer Tool Suite
PAC-Designer software is the tool suite for the design and verification
tool of Lattice mixed signal devices. The PAC-Designer software is a
complete design environment, including everything needed for design,
implementation, simulation and programming of supported devices.
Pricing and Availability
Lattice's PAC-Designer software for Windows is available now at no charge
for download from the Lattice website, www.latticesemi.com/products/designsoftware/pacdesigner
About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD,
programmable Power
Management and Programmable Clock
solutions. For more information, visit www.latticesemi.com
Lattice Semiconductor Corporation, Lattice (& design), L (& design),
PAC-Designer, ispPAC, ispClock and specific product designations are either
registered trademarks or trademarks of Lattice Semiconductor Corporation or
its subsidiaries in the United States and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for
identification purposes only and may be trademarks of their respective
holders.
EDITORIAL/READER CONTACT:
Brian Kiernan
Corporate Communications Manager
Lattice Semiconductor Corporation
503-268-8739 voice
503-268-8193 fax
brian.kiernan@latticesemi.com
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