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Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC PlatformsSAN JOSE, Calif., Sept. 22, 2016 /PRNewswire/ -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms. As a result of the joint work, Cadence® digital, signoff and custom/analog tools have achieved certification for the latest Design Rule Manual (DRM) and SPICE for the TSMC 7nm process. In addition, a new process design kit (PDK) enabling customers to achieve optimal power, performance and area (PPA) is now available. Cadence has also made enhancements to the 7nm Custom Design Reference Flow and library characterization flow. These design tool advancements have enabled Cadence to accelerate initial deliveries of its high-speed SerDes and low-latency DDR IP cores to leading customers, with test chips expected to tape out in the fourth quarter of this year. These products represent the first of a comprehensive portfolio of application-optimized 7nm solutions to be developed by Cadence. To learn more about the Cadence digital and signoff advanced node solutions, please visit www.cadence.com/go/tsmc7nmds. For information on the Cadence custom/analog advanced node solutions, visit www.cadence.com/go/tsmc7nmca. For information on Cadence IP advanced node solutions, please visit www.cadence.com/go/tsmc7nmip. 7nm Tool Certification Cadence provides a fully integrated and stable TSMC 7nm flow, from implementation to final signoff. The digital implementation and signoff tools certified include Innovus™ Implementation System, Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System and Layout-Dependent Effect (LDE) Electrical Analyzer. Support for the 7nm mobile and HPC platform, available in November 2016, includes via-pillar and clock mesh handling and bus routing, as well as support for the high-performance library to deliver targeted PPAand mitigated electro-migration (EM), which enable customers to reduce iterations and achieve their cost and performance objectives. In addition, both companies are working on enabling via pillar what-if analysis in Genus™ Synthesis Solution and continuing to optimize pin access and cut metal handling in Innovus Implementation System. The certified custom/analog tools include Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and Spectre Circuit Simulator, as well as the Virtuoso® custom IC advanced-node platform. The Spectre suite delivers circuit simulation to support advanced-node device models with self-heating and reliability effects. The Virtuoso suite is further optimized for 7nm custom design implementation and provides innovative in-design to signoff flows. 7nm CDRF Enhancements 7nm Library Characterization Tool Flow Enhancements Optimized 7nm IP Development "TSMC's process innovations require ongoing tool and IP enhancements so that we can deliver optimal solutions for advanced-node customers," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. "Our joint work supports the needs of early customers who are transitioning to the 7nm node to maintain leadership in the mobile and HPC markets." "We worked closely with Cadence to certify the tools and integrated flow for 7nm designs, which will help customers achieve PPA objectives and create designs with confidence," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "By working together with Cadence, we are able to actively engage with customers on advanced 7nm designs to enable them to maximize the benefits of this leading-edge technology." About Cadence This press release contains certain forward-looking statements that are based on our current expectations and involve numerous risks and uncertainties that may cause these forward-looking statements to be inaccurate. Risks that may cause these forward-looking statements to be inaccurate include, among others, the risks detailed from time-to-time in our U.S. Securities and Exchange Commission filings and reports, including, but not limited to, our most recent quarterly report on Form 10-Q and our annual report on Form 10-K. We do not intend to update the information contained in this press release. © 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. For more information, please contact: Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO
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