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Astera Labs Verifies Its System-Aware PCI Express® 5.0 Smart Retimer Using Avery Design Systems PCIe® 5.0 Verification IPAvery Design Systems, leader in functional verification solutions today announced that Astera Labs successfully utilized Avery's Peripheral Component Interconnect PCI (News - Alert) Express® (PCIe®) 5.0 Verification IP and services to verify its breakthrough system-aware PCIe 5.0 Smart Retimer. The Avery PCIe 5.0 VIP supports models and testsuites for the newly ratified PCI 5.0 specification including latest enhancements for retimers operating at 32 GT/s and the alternate protocol mode of operation. "At Astera Labs, our priority is to deliver Smart Retimer products that fully meet PCIe specification and achieve plug-and-play interoperation," said Jitendra Mohan, chief executive officer at Astera Labs. "Avery PCIe 5.0 VIP is a critical tool in our verification environment to thoroughly test our design and deliver a high quality product to our customers." "The PCIe 5.0 specification delivers unprecedented performance levels at 32 GT/s while extending reach of I/O system topologies and breadth of solutions spanning HPC to mobile/IoT applications," said Al Yanes, PCI-SIG chairman and president. "he PCIe verification ecosystem space is so crucial to our members, as it helps them to develop chips and systems with highest quality, interoperability, and compliance.
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