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U.S. Patents Awarded to Inventors in Oregon (Jan. 30)
[January 30, 2013]

U.S. Patents Awarded to Inventors in Oregon (Jan. 30)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., Jan. 30 -- The following federal patents were awarded to inventors in Oregon.

*** J. Frank Schmidt & Son Assigned Patent ALEXANDRIA, Va., Jan. 30 -- J. Frank Schmidt & Son, Boring, Ore., has been assigned a patent (PP23,361) developed by Keith S. Warren, Gresham, Ore., for a "sugar maple tree named 'JFS-Caddo2'." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A variety of sugar maple which combines intense bright red fall color, an upright oval to slightly pyramidal canopy shape, and foliage that is dark green, moderately resistant to powdery mildew, and very resistant to heat." The patent application was filed on Dec. 6, 2010 (12/928,219). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=PP23,361&OS=PP23,361&RS=PP23,361 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** International Business Machines Assigned Patent for Preventing Execution of Processes Responsive to Changes in the Environment ALEXANDRIA, Va., Jan. 30 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,365,185) developed by Mythili K. Bobak, Lagrangeville, N.Y., Tim A. McConnell, Lexington, Ky., and Michael D. Swanson, Springfield, Ore., for a "preventing execution of processes responsive to changes in the environment." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Processes are programmatically categorized into a plurality of categories, which are prioritized. Serialization is used to control execution of the processes of the various categories. The serialization ensures that processes of higher priority categories are given priority in execution. This includes temporarily preventing processes of lower priority categories from being executed." The patent application was filed on Dec. 28, 2007 (11/965,978). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,365,185&OS=8,365,185&RS=8,365,185 Written by Satyaban Rath; edited by Hemanta Panigrahi.

*** Intel Assigned Patent for Sink Device Addressing Mechanism ALEXANDRIA, Va., Jan. 30 -- Intel, Santa Clara, Calif., has been assigned a patent (8,364,797) developed by Srikanth Kambhatla, Portland, Ore., for a "sink device addressing mechanism." The abstract of the patent published by the U.S. Patent and Trademark Office states: "In general, in one aspect, the disclosure describes a method to assign unique addresses to each sink device in a content network based on port numbers of a source and branch devices in the network. Sink devices connected to a port on the source or the branch devices are assigned a corresponding port number as a sink address. Branch devices connected to a port on the source or higher level branch devices have a corresponding port number prepended to the previously assigned sink addresses." The patent application was filed on May 26, 2010 (12/787,752). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,64,797.PN.&OS=PN/83,64,797&RS=PN/83,64,797 Written by Amal Ahmed; edited by Jaya Anand.


*** Intel Assigned Patent ALEXANDRIA, Va., Jan. 30 -- Intel, Santa Clara, Calif., has been assigned a patent (8,364,863) developed by Steven B. McGowan, Portland, Ore., for a "method and apparatus for universal serial bus (USB) command queuing." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for improving performance of mass storage class devices accessible via a Universal Serial Bus (USB) is presented. Performance is improved by providing support in a USB host to allow command queuing and First-Party DMA (FPDMA) to be supported in the mass storage class devices." The patent application was filed on Dec. 18, 2008 (12/317,019). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,64,863.PN.&OS=PN/83,64,863&RS=PN/83,64,863 Written by Amal Ahmed; edited by Jaya Anand.

*** Cisco Technology Assigned Patent ALEXANDRIA, Va., Jan. 30 -- Cisco Technology, San Jose, Calif., has been assigned a patent (8,364,877) developed by four co-inventors for implementing gang interrupts. The co-inventors are Shrijeet Mukherjee, Fremont, Calif., Michael Brian Galles, Los Altos, Calif., David Scott Feldman, McMinnville, Ore., and J. Bradley Smith, San Jose, Calif.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method includes receiving a first interrupt request from a first device instance of a plurality of device instances. The first interrupt request is requesting an interrupt of a processor. The method also includes updating a bit vector based on the first interrupt request. The bit vector comprises a plurality of bits representing an accumulation of interrupt requests. The method further includes generating a gang interrupt comprising the updated bit vector. The method also includes transmitting the gang interrupt to call a first device driver associated with the first interrupt request based on the bits in the bit vector." The patent application was filed on Dec. 16, 2009 (12/639,558). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,64,877.PN.&OS=PN/83,64,877&RS=PN/83,64,877 Written by Amal Ahmed; edited by Jaya Anand.

*** Intel Assigned Patent for Delegating a Poll Operation to another Device ALEXANDRIA, Va., Jan. 30 -- Intel, Santa Clara, Calif., has been assigned a patent (8,364,862) developed by four co-inventors for "delegating a poll operation to another device." The co-inventors are Michael J. Espig, Newberg, Ore., Zhen Fang, Portland, Ore., Ravishankar Iyer, Hillsboro, Ore., and David J. Harriman, Portland, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed." The patent application was filed on June 11, 2009 (12/482,614). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,64,862.PN.&OS=PN/83,64,862&RS=PN/83,64,862 Written by Amal Ahmed; edited by Jaya Anand.

*** Citrix Systems Assigned Patent ALEXANDRIA, Va., Jan. 30 -- Citrix Systems, Fort Lauderdale, Fla., has been assigned a patent (8,364,785) developed by Robert Plamondon, Blodgett, Ore., for "systems and methods for domain name resolution interception caching." The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present solution provides a variety of techniques for accelerating and optimizing network traffic, such as HTTP based network traffic. The solution described herein provides techniques in the areas of proxy caching, protocol acceleration, domain name resolution acceleration as well as compression improvements. In some cases, the present solution provides various prefetching and/or prefreshening techniques to improve intermediary or proxy caching, such as HTTP proxy caching. In other cases, the present solution provides techniques for accelerating a protocol by improving the efficiency of obtaining and servicing data from an originating server to server to clients. In another cases, the present solution accelerates domain name resolution more quickly. As every HTTP access starts with a URL that includes a hostname that must be resolved via domain name resolution into an IP address, the present solution helps accelerate HTTP access. In some cases, the present solution improves compression techniques by prefetching non-cacheable and cacheable content to use for compressing network traffic, such as HTTP. The acceleration and optimization techniques described herein may be deployed on the client as a client agent or as part of a browser, as well as on any type and form of intermediary device, such as an appliance, proxying device or any type of interception caching and/or proxying device." The patent application was filed on Dec. 9, 2009 (12/634,339). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=83,64,785.PN.&OS=PN/83,64,785&RS=PN/83,64,785 Written by Amal Ahmed; edited by Jaya Anand.

*** Intel Assigned Patent for Methods and Apparatus for Protecting Data ALEXANDRIA, Va., Jan. 30 -- Intel, Santa Clara, Calif., has been assigned a patent (8,364,975) developed by Mohan J. Kumar, Aloha, Ore., and Shay Gueron, Haifa, Israel, for "methods and apparatus for protecting data." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An augmented boot code module includes instructions to be executed by a processing unit during a boot process. The augmented boot code module also includes an encrypted version of a cryptographic key that can be decrypted with a cryptographic key that remains in the processing unit despite a reset of the processing unit. In one embodiment, the processing unit may decrypt the encrypted version of the cryptographic key and then use the decrypted key to establish a protected communication channel with a security processor, such as a trusted platform module (TPM). Other embodiments are described and claimed." The patent application was filed on Dec. 29, 2006 (11/648,472). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,364,975.PN.&OS=PN/8,364,975&RS=PN/8,364,975 Written by Kusum Sangma; edited by Anand Kumar.

*** International Business Machines Assigned Patent for Selective Power Reduction of Memory Hardware ALEXANDRIA, Va., Jan. 30 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,364,995) developed by four co-inventors for a "selective power reduction of memory hardware." The co-inventors are Gerrit Huizenga, Portland, Ore., Vivek Kashyap, Beaverton, Ore., Badari Pulavarty, Beaverton, Ore., and Russell H. Weight, Hillsboro, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Managing delivery of power to one or more hardware memory devices in a computer system. The computer system is configured with a processor and at least two hardware memory devices. A temperature monitor tool is employed to monitor the hardware memory devices. Management of an addressable subset of the hardware memory devices is employed in response to the monitored temperature reading." The patent application was filed on April 30, 2012 (13/459,327). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,364,995.PN.&OS=PN/8,364,995&RS=PN/8,364,995 Written by Kusum Sangma; edited by Anand Kumar.

*** Intel Assigned Patent for Dynamic Generation of Integrity Manifest for Run-time Verification of Software Program ALEXANDRIA, Va., Jan. 30 -- Intel, Santa Clara, Calif., has been assigned a patent (8,364,973) developed by four co-inventors for a "dynamic generation of integrity manifest for run-time verification of software program." The co-inventors are Hormuzd Khosravi, Portland, Ore., David Durham, Hillsboro, Ore., Prashant Dewan, Hillsboro, Ore., Ravi Sahita, Beaverton, Ore., Uday R. Savagaonkar, Beaverton, Ore., and Men Long, Hillsboro, Ore.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A measurement engine generates an integrity manifest for a software program and uses it to perform active platform observation. The integrity manifest indicates an integrity check value for a section of the program's code. The measurement engine computes a comparison value on the program's image in memory and determines if the comparison value matches the expected integrity check value. If the values do not match, the program's image is determined to be modified, and appropriate remedial action may be triggered." The patent application was filed on Dec. 31, 2007 (11/967,928). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,364,973.PN.&OS=PN/8,364,973&RS=PN/8,364,973 Written by Kusum Sangma; edited by Anand Kumar.

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