[May 26, 2012] Tezzaron Semiconductor Assigned Patent Tweet (Targeted News Service Via Acquire Media NewsEdge) By Targeted News Service ALEXANDRIA, Va., May 26 -- Tezzaron Semiconductor, Naperville, Ill., has been assigned a patent (8,183,127) developed by Robert Patti, Warrenville, Ill., Sangki Hong, Singapore, and Ramasamy Chockalingam, Singapore, for a "method for bonding wafers to produce stacked integrated circuits." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP." The patent application was filed on May 24, 2010 (12/786,273). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,183,127&OS=8,183,127&RS=8,183,127 Written by Satyaban Rath; edited by Hemanta Panigrahi. SR0526HP0526-742061 (c) 2012 Targeted News Service [ Back To TMCnet.com's Homepage ]