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U.S. Patents Awarded to Inventors in California (March 14)(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service Targeted News Service ALEXANDRIA, Va., March 14 -- The following federal patents were awarded to inventors in California. *** Oracle America Assigned Patent for Method and Apparatus for Synthesizing Hardware Counters from Performance Sampling ALEXANDRIA, Va., March 14 -- Oracle America, Redwood City, Calif., has been assigned a patent (8,136,124) developed by Nicolai Kosche, San Francisco, and Kenneth Tracton, Palo Alto, Calif., for a "method and apparatus for synthesizing hardware counters from performance sampling." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for performance monitoring may use data collected from a hardware event agent comprising a hardware sampling mechanism and/or one or more hardware counters to increment one or more synthesized performance counters by an amount dependent on an expression involving the collected data. Each synthesized performance counter may be configured to count events of a different type and may comprise a machine addressable storage location. The event types may include various memory references or misses, branches, branch mispredictions, or any other event of interest in performance monitoring. The hardware event agent may comprise one or more instruction counters, cycle counters, timers, or other hardware performance counters. One hardware performance counter may be used in a time-multiplexed or data-multiplexed manner to monitor events of multiple event types. The hardware sampling mechanism may return a statistical packet for sampled instructions, which may be examined to determine the event type." The patent application was filed on Jan. 18, 2007 (11/624,526). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,124&OS=8,136,124&RS=8,136,124 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Walker Digital Assigned Patent ALEXANDRIA, Va., March 14 -- Walker Digital, Stamford, Conn., has been assigned a patent (8,136,133) developed by seven co-inventors for "methods and systems for broadcasting modified live media." The co-inventors are Jay S. Walker, Ridgefield, Conn., Evan Walker, Ridgefield, Conn., Russell P. Sammon, San Francisco, Zachary T. Smith, Norwalk, Conn., Jeffrey Y. Hayashida, San Francisco, Renny S. Tallanchich, London, and Robert C. Tedesco, Fairfield, Conn. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and systems are presented for broadcasting a modified live media feed of an event. In an embodiment, the method includes receiving a live media feed at a broadcast computer from one or more recording devices, wherein the live media feed includes real time occurrences of a live event. The live media feed is broadcast after a predetermined delay, and the method includes identifying, during monitoring of the live event, a portion of the live event that is suitable for application of a modification effect. The process also includes the broadcast computer applying the modification effect to a portion of the live media feed corresponding to the identified portion of the live event, and then broadcasting the modified live media feed." The patent application was filed on Nov. 13, 2008 (12/270,455). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,133&OS=8,136,133&RS=8,136,133 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Oracle America Assigned Patent ALEXANDRIA, Va., March 14 -- Oracle America, Redwood City, Calif., has been assigned a patent (8,136,101) developed by Raj Prakash, Saratoga, Calif., for a "threshold search failure analysis." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A value range for a code development option, which results in an error when applied to a given code, can be automatically searched to intelligently identify a threshold for the error within the value range. Instead of completely abandoning the optimizations offered by a code development option with a value range, the code development option as applied to a given code can be limited to a subrange of the value range, thus imbuing the given code with at least the optimizations offered by the code development option with the subrange. A failure analysis tool searches, for example according to binary search, a value range. Subranges are applied to the given code and results examined to influence successive selections of subranges. Eventually, a threshold, if any, is discovered that separates a subrange that does not result in error from a subrange that results in error." The patent application was filed on Nov. 4, 2005 (11/267,746). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,101&OS=8,136,101&RS=8,136,101 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Broadcom Assigned Patent ALEXANDRIA, Va., March 14 -- Broadcom, Irvine, Calif., has been assigned a patent (8,136,162) developed by Bora Akyol, San Jose, Calif., and Puneet Agarwal, Cupertino, Calif., for an "intelligent network interface controller." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A network interface device includes a security database and a security services engine. The security database is configured to store patterns corresponding to predetermined malware. The security services engine is configured to compare data to be transmitted through a network to the patterns stored in the security database, and the security database is configured to receive updated patterns from the network." The patent application was filed on Aug. 31, 2006 (11/513,873). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,162&OS=8,136,162&RS=8,136,162 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Check Point Software Technologies Assigned Patent ALEXANDRIA, Va., March 14 -- Check Point Software Technologies, Redwood City, Calif., has been assigned a patent (8,136,155) developed by Gregor P. Freund, San Francisco, for a "security system with methodology for interprocess communication control." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A security system with methodology for interprocess communication control is described. In one embodiment, a method for controlling interprocess communication is provided that includes steps of: defining rules indicating which system services a given application can invoke; trapping an attempt by a particular application to invoke a particular system service; identifying the particular application that is attempting to invoke the particular system service; and based on identity of the particular application and on the rules indicating which system services a given application can invoke, blocking the attempt when the rules indicate that the particular application cannot invoke the particular system service." The patent application was filed on Sept. 12, 2003 (10/605,189). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,155&OS=8,136,155&RS=8,136,155 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Check Point Software Technologies Assigned Patent ALEXANDRIA, Va., March 14 -- Check Point Software Technologies, Redwood City, Calif., has been assigned a patent (8,136,149) developed by Gregor Paul Freund, San Francisco, for a "security system with methodology providing verified secured individual end points." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A security system with methodology providing verified secured individual end points is described. In one embodiment, for example, a method of the present invention is described for controlling access to a particular application, the method comprises steps of: defining firewall rules specifying filtering conditions for incoming network traffic, the firewall rules including an application attribute that allows individual rules to be associated with specific applications, the firewall rules also including extended attributes that allow specification of additional conditions that a given end point is required to meet; intercepting incoming network traffic destined for a particular application for which a particular application-specific firewall rule has been created; examining the extended attributes for the particular application-specific firewall rule, for determining what additional conditions the given end point must comply with in order to communicate with the particular application; if the given end point complies with the additional conditions, allowing the end point to communicate with the particular application; and otherwise blocking the end point to prevent communication with the particular application." The patent application was filed on March 29, 2005 (10/907,331). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,149&OS=8,136,149&RS=8,136,149 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Intel Assigned Patent ALEXANDRIA, Va., March 14 -- Intel, Santa Clara, Calif., has been assigned a patent (8,136,112) developed by Tatiana Shpeisman, Menlo Park, Calif., Ali-Reza Adl-Tabatabai, Santa Clara, Calif., and Brian Murphy, Mountain View, Calif., for a "thread synchronization via selective modification of stored states of pending optimistically balanced lock releases having previous lock owner and validity flag." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Thread synchronization methods and apparatus for managed run-time environments are disclosed. An example method to maintain state information for optimistically balanced synchronization of a lock of an object in a managed runtime environment disclosed herein comprises storing state information comprising a state of each pending optimistically balanced release operation corresponding to each pending optimistically balanced synchronization to be performed on the lock of the object, each pending optimistically balanced synchronization comprising respective paired acquisition and release operations between which an unknown number of unpaired locking operations are to occur, and modifying a first stored state of a first pending optimistically balanced release operation when a subsequent unpaired locking operation is performed on the lock, but not modifying any stored state of any pending optimistically balanced release, including the first stored state of a first pending optimistically balanced release operation, when a subsequent optimistically balanced synchronization is performed on the lock." The patent application was filed on Sept. 14, 2009 (12/559,254). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,112&OS=8,136,112&RS=8,136,112 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Ericsson Television Assigned Patent ALEXANDRIA, Va., March 14 -- Ericsson Television, Duluth, Ga., has been assigned a patent (8,136,142) developed by five co-inventors for a "centralized content management system for managing distribution of packages to video service providers." The co-inventors are James H. Alexander, Highlands Ranch, Colo., Michael Petrusis, Santa Monica, Calif., Yoichi Yamamoto, Los Angeles, Sumanth Gentela, Norcross, Ga., and Ashish Ghanate, Norcross, Ga. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A centralized Content Management System ("CCMS") facilitates management of packages comprising assets comprising meta-data and associated content of video programs for distribution to various types of service providers and equipment locations therein. The CCMS can receive meta-data and associated content, normalize the meta-data according to various formats based on various rules depending on where the meta-data and contents are to be distributed, and the distribute the content. The CCMS has various capabilities for managing packages, including adapting the meta-data and content for different types of equipment or individual locations based on rules for that service provider, thus providing an automated system reducing error and time in distributing video assets to a number of locations." The patent application was filed on July 2, 2009 (12/496,738). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,142&OS=8,136,142&RS=8,136,142 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Bank of America Assigned Patent ALEXANDRIA, Va., March 14 -- Bank of America, Charlotte, N.C., has been assigned a patent (8,136,148) developed by five co-inventors for a "reusable authentication experience tool." The co-inventors are Pavan Chayanam, Walnut Creek, Calif., Todd Inskeep, Charlotte, N.C., Eric William Miller, Issaquah, Wash., Clay Newton, Napa, Canada, and David Charles Shroyer, Matthews, N.C. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A reusable authentication component may be integrated into a web page to communicate with an authentication server and authenticate a user to the web page. The reusable authentication component may implement a complex authentication process, including multiple user interfaces to receive multiple assurances of user identity and user confirmation of previously stored mutual authentication data. The authentication process may be performed by the authentication component without refreshing or redirecting the parent web page until completion of a successful user authentication, after which the parent web page may receive authentication data and refresh to provide user specific and/or secure user data on the web page." The patent application was filed on April 9, 2005 (12/100,170). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,148&OS=8,136,148&RS=8,136,148 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Google Assigned Patent ALEXANDRIA, Va., March 14 - Google, Mountain View, Calif., has been assigned a patent (8,136,167) developed by Richard Carl Gossweiler III, Sunnyvale, Calif., Shumeet Baluja, Leesburg, Va., and Maryam Kamvar, San Francisco, for "systems and methods for providing image feedback." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A computer-implemented method may include receiving, over a network, an image from an image capture device, determining an image adjustment to the image, and communicating, over the network, the image adjustment to the image capture device." The patent application was filed on Oct. 20, 2008 (12/254,312). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,167&OS=8,136,167&RS=8,136,167 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Adobe Systems Assigned Patent ALEXANDRIA, Va., March 14 -- Adobe Systems, San Jose, Calif., has been assigned a patent (8,136,127) developed by five co-inventors for a "system and method for linearly managing client-server communication." The co-inventors are Slavik Lozben, San Francisco, Pritham Shetty, Los Altos, Calif., Jonathan Gay, Mill Valley, Calif., Stephen Cheng, Foster City, Calif., and Bradley Edelman, San Francisco. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Representative embodiments are disclosed of a system and method for linearly exposing client-server interaction comprising interpreting a function command representing a first group of sequential action requests to an integrated multimedia communication server (iMCS), sequentially transmitting the first group of sequential action requests from an interactive multimedia runtime (iMR) client to the iMCS, wherein a next sequential action request of the first group is transmitted to the iMCS prior to receiving a response message from the iMCS associated with a previous sequential action request of the first group, queuing response messages received from the iMCS, and handling the queued response messages." The patent application was filed on June 29, 2007 (11/771,849). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,127&OS=8,136,127&RS=8,136,127 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Faust Communications Assigned Patent ALEXANDRIA, Va., March 14 -- Faust Communications, Las Vegas, has been assigned a patent (RE43,235) developed by Takatoshi Ishii, Sunnyvale, Calif., Edmund Cheung, Palo Alto, Calif., and Sherwood Brannon, Sebastian, Fla., for a "single-block virtual frame buffer translated to multiple physical blocks for multi-block display refresh generator." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes." The patent application was filed on May 28, 2010 (12/789,856). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=RE43,235&OS=RE43,235&RS=RE43,235 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Oracle International Assigned Patent ALEXANDRIA, Va., March 14 -- Oracle International, Redwood Shores, Calif., has been assigned a patent (8,136,150) developed by Don L. Hayler, Palo Alto, Calif., and Daniel Vu, Lafayette, Calif., for "user role mapping in web applications." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Roles and policies are used to provide display and access to data in a flexible manner. Users and/or web applications can be mapped to user roles that dictate which displays or other application resources are available to the user or application. Roles are assigned to web applications individually, allowing for user roles to be used without requiring an independent mapping of users to roles. In some cases, application roles can be centrally managed, so that presentation systems also avoid the need for an independent mapping of user or application roles." The patent application was filed on Nov. 2, 2010 (12/917,764). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,150&OS=8,136,150&RS=8,136,150 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Facebook Assigned Patent ALEXANDRIA, Va., March 14 -- Facebook, Palo Alto, Calif., has been assigned a patent (8,136,145) developed by Dave Fetterman, San Francisco, and Adam D'Angelo, Mountain View, Calif., for a "network authentication for accessing social networking system information by a third party application." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Exemplary systems and methods for network authentication are provided. Exemplary systems include an application program interface configured for receiving a request for an authentication code, a code generator in communication with the application program interface, the code generator configured to generate the authentication code, and the application program interface further configured to receive the generated authentication code and allow an application to communicate digital data with a web-based social network. Further systems include the generated authentication code being received from a network device without an Internet browser and the received generated authentication code allowing an application to communicate digital data with a web-based social network for an extended period of time. Exemplary methods include receiving a request for an authentication code, generating the authentication code, receiving the generated authentication code, and allowing an application to communicate digital data with a web-based social network." The patent application was filed on March 13, 2008 (12/077,070). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,145&OS=8,136,145&RS=8,136,145 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** TIBCO Software Assigned Patent ALEXANDRIA, Va., March 14 -- TIBCO Software, Palo Alto, Calif., has been assigned a patent (8,136,109) developed by four co-inventors for a "delivery of data and formatting information to allow client-side manipulation." The co-inventors are Lucas Birdeau, San Francisco, Clifford Yeh, Los Angeles, Michael Peachey, San Mateo, Calif., and Kevin Hakman, San Francisco. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Delivering data and formatting information includes delivering object definition files from a server to a client; generating definitions and object instantiations at a client using JavaScript or another simple browser-interpreted language, for objects relating to data modeling and presentation; and presenting data using those objects at the client, using a web browser without a separate runtime environment or application plug-in, but maintaining substantial state at the web browser regarding the data itself and the format for its presentation. Definition files are modified to provide object properties consistent with a full object-oriented language, including for example hierarchical inheritance of object properties. Code ballooning generates definitions and individual instantiations, with the effect that a very large amount of DHTML, or another markup or presentation definition language for use with the application, can be generated from relatively small aggregate size of definition files communicated from the server to the client." The patent application was filed on Oct. 22, 2002 (10/278,728). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,109&OS=8,136,109&RS=8,136,109 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Graphical Message Format Builder ALEXANDRIA, Va., March 14 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,136,121) developed by four co-inventors for a "graphical message format builder." The co-inventors are Mihai Cristian Birloncea, Richmond Hill, Canada, Shelley Lau, Scarborough, Calif., Martin Leclerc, Toronto, and Alfred Chun Yang, Richmond Hill, Canada. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A graphical message format builder facilitates a user in building message formats by using format elements from a format editor palette which are inserted into a message format definition in a graphical editing pane. Each format element is served as a building block of a message format which in turn is used to construct the message. A format hierarchy view allows a visualization of the data mapping to the message format to be seen." The patent application was filed on March 16, 2005 (10/907,008). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,121&OS=8,136,121&RS=8,136,121 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Google Assigned Patent for User-level Segmentation Mechanism that Facilitates Safely Executing Untrusted Native Code ALEXANDRIA, Va., March 14 -- Google, Mountain View, Calif., has been assigned a patent (8,136,158) developed by David C. Sehr, Cupertino, Calif., J. Bradley Chen, Los Gatos, Calif., and Bennet S. Yee, Mountain View, Calif., for an "user-level segmentation mechanism that facilitates safely executing untrusted native code." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system that uses segmentation to safely execute native code. This system includes a processing element that executes the native code and a memory which stores code and data for the processing element. The processing element includes a segmentation mechanism which limits the native code executing on the processing element to accessing a specified segment of memory. The processing element also includes an instruction-processing unit, which is configured to execute a user-level instruction that causes the segmentation mechanism to limit memory accesses by the native code to the specified segment of the memory." The patent application was filed on Aug. 29, 2008 (12/202,083). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,158&OS=8,136,158&RS=8,136,158 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Google Assigned Patent ALEXANDRIA, Va., March 14 -- Google, Mountain View, Calif., has been assigned a patent (8,136,102) developed by four co-inventors for "systems and methods for compiling an application for a parallel-processing computer system." The co-inventors are Matthew N. Papakipos, Palo Alto, Calif., Brian K. Grant, Cupertino, Calif., Christopher G. Demetriou, Redwood City, Calif., and Morgan S. McGuire, Sunnyvale, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications." The patent application was filed on March 5, 2007 (11/714,582). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,102&OS=8,136,102&RS=8,136,102 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Weeks Wholesale Rose Grower Assigned Patent ALEXANDRIA, Va., March 14 -- Weeks Wholesale Rose Grower, Pomona, Calif., has been assigned a patent (PP22,571) developed by Thomas F. Carruth, Altadena, Calif., for a "floribunda rose plant named 'WEKcharlie'." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A new variety of Floribunda rose suitable for garden decoration, having flowers of red velvet coloration." The patent application was filed on Nov. 22, 2010 (12/927,751). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=PP22,571&OS=PP22,571&RS=PP22,571 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** International Business Machines Assigned Patent for Combining Static and Dynamic Compilation to Remove Delinquent Loads ALEXANDRIA, Va., March 14 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,136,103) developed by four co-inventors for a "combining static and dynamic compilation to remove delinquent loads." The co-inventors are Gheorghe C. Cascaval, Carmel, N.Y., Yaoqing Gao, North York, Canada, Allan H. Kielstra, Ajax, Calif., and Kevin A. Stoodley, Richmond Hill, Canada. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for combined static and dynamic compilation of program code to remove delinquent loads can include statically compiling source code into executable code with instrumented sections each being suspected of including a delinquent load, and also into a separate intermediate language representation with annotated portions each corresponding to one of the instrumented sections. The method also can include executing the instrumented sections repeatedly and monitoring cache misses for each execution. Finally, the method can include dynamically recompiling selected ones of the instrumented sections using corresponding ones of the annotated portions of the separate intermediate language representation only after a threshold number of executions of the selected ones of the instrumented sections, each recompilation include a pre-fetch directive at a pre-fetch distances tuned to avoid the delinquent load." The patent application was filed on March 28, 2008 (12/058,172). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,103&OS=8,136,103&RS=8,136,103 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Bay City Flower Assigned Patent ALEXANDRIA, Va., March 14 -- Bay City Flower, Half Moon Bay, Calif., has been assigned a patent (PP22,575) developed by Harrison M. Higaki, San Mateo, Calif., for a "hydrangea plant named 'Galilee'." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A new and distinct cultivar of Hydrangea macrophylla (Thunb.) named `Galilee` originated as a controlled cross between Hydrangea macrophylla (Thunb.) True Blue - U.S. Plant Pat. No. 18,593 (the seed parent), and the unpatented commercial variety Hydrangea macrophylla (Thunb.) `Mathilda Gutges` (the pollen parent). The cultivar `Galilee` can be blue or pink depending on the acidity of the soil. The new cultivar is characterized by its sturdy growth habit and its ability to produce blue pigmentation with relatively low levels of soil amendments. The new cultivar has showy inflorescences with large florets." The patent application was filed on Aug. 19, 2010 (12/806,808). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=PP22,575&OS=PP22,575&RS=PP22,575 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** SonicWALL Assigned Patent ALEXANDRIA, Va., March 14 -- SonicWALL, San Jose, Calif., has been assigned a patent (8,136,143) developed by Clifford L. Hannel, Westlake Village, Calif., Laurence R. Lipstone, Westlake Village, Calif., and David S. Schneider, Westlake Village, Calif., for a generalized policy server. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A scalable access filter that is used together with others like it in a virtual private network to control access by users at clients in the network to information resources provided by servers in the network. Each access filter use a local copy of an access control database to determine whether an access request made by a user. Changes made by administrators in the local copies are propagated to all of the other local copies. Each user belongs to one or more user groups and each information resource belongs to one or more information sets. Access is permitted or denied according to of access policies which define access in terms of the user groups and information sets. Access is further permitted only if the trust levels of a mode of identification of the user and of the path in the network by which the access is made are sufficient for the sensitivity level of the information resource. If necessary, the access filter automatically encrypts the request with an encryption method whose trust level is sufficient." The patent application was filed on Aug. 4, 2010 (12/850,587). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,143&OS=8,136,143&RS=8,136,143 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Intersil Americas Assigned Patent ALEXANDRIA, Va., March 14 -- Intersil Americas, Milpitas, Calif., has been assigned a patent (RE43,236) developed by Hoa Vu, Milpitas, Calif., Teck-Boon Serm, Freemont, Calif., and Bhupendra K. Ahuja, Freemont, Calif., for an "automatic circuit and method for temperature compensation of oscillator frequency variation over temperature for a real time clock chip." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An automatic temperature compensated real-time clock (RTC) chip includes a clock portion having a crystal oscillator block including crystal compensation circuitry adapted to be coupled to a crystal. The crystal compensation circuitry includes a non-linear capacitor DAC including a plurality of load capacitors, wherein the load capacitors have respective switches which switch respective ones of the load capacitors to change a parallel resonance frequency (fp) generated by the oscillator block. The capacitor DAC is arranged so that Analog Trimming (ATR) bits received cause an arrangement of the switches to provide a non-linear change in overall load capacitance to result in a linear relationship between fp and the ATR bits. A temperature sensor block is coupled to the crystal for measuring a temperature of at least the crystal. An A/D converter is coupled to the temperature sensor for outputting a digital temperature signal representative of the temperature of the crystal. A DSP engine receives the digital temperature signal and calculates frequency correction needed to correct for frequency inaccuracy and determines a bit sequence including the ATR bits appropriate to achieve the frequency correction." The patent application was filed on May 13, 2010 (12/779,885). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=RE43,236&OS=RE43,236&RS=RE43,236 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** LSI Assigned Patent ALEXANDRIA, Va., March 14 -- LSI, Milpitas, Calif., has been assigned a patent (8,136,161) developed by Christopher Hamlin, Los Gatos, Calif., for a "3-prong security/reliability/real-time distributed architecture of information handling system." The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried nucleus is in operation, and a trusted authority for generating a secure protocol. The secure protocol controls the operation of the buried nucleus." The patent application was filed on Feb. 3, 2010 (12/699,463). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,161&OS=8,136,161&RS=8,136,161 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Google Assigned Patent for Systems and Methods for Determining Compute Kernels for an Application in a Parallel-processing Computer System ALEXANDRIA, Va., March 14 -- Google, Mountain View, Calif., has been assigned a patent (8,136,104) developed by four co-inventors for "systems and methods for determining compute kernels for an application in a parallel-processing computer system." The co-inventors are Matthew N. Papakipos, Palo Alto, Calif., Brian K. Grant, Cupertino, Calif., Morgan S. McGuire, Sunnyvale, Calif., and Christopher G. Demetriou, Redwood City, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications." The patent application was filed on March 5, 2007 (11/714,592). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,104&OS=8,136,104&RS=8,136,104 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Cadence Design Systems Assigned Patent for Method and Mechanism for Identifying and Tracking Shape Connectivity ALEXANDRIA, Va., March 14 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,136,060) developed by Eric Nequist, Monte Sereno, Calif., for a "method and mechanism for identifying and tracking shape connectivity." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels." The patent application was filed on Dec. 29, 2009 (12/648,843). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,060&OS=8,136,060&RS=8,136,060 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Microsoft Assigned Patent for Architectural Support for Software-based Protection ALEXANDRIA, Va., March 14 -- Microsoft, Redmond, Wash., has been assigned a patent (8,136,091) developed by Ulfar Erlingsson, San Francisco, Martin Abadi, Palo Alto, Calif., and Mihai-Dan Budiu, Sunnyvale, Calif., for an "architectural support for software-based protection." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Instruction set architecture (ISA) extension support is described for control-flow integrity (CFI) and for XFI memory protection. ISA replaces CFI guard code with single instructions. ISA support is provided for XFI in the form of bounds-check instructions. Compared to software guards, hardware support for CFI and XFI increases the efficiency and simplicity of enforcement. In addition, the semantics for CFI instructions allows more precise static control-flow graph encodings than were possible with a prior software CFI implementation." The patent application was filed on Jan. 31, 2007 (11/700,451). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,091&OS=8,136,091&RS=8,136,091 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Synopsys Assigned Patent ALEXANDRIA, Va., March 14 -- Synopsys, Mountain View, Calif., has been assigned a patent (8,136,077) developed by Larry E. McMurchie, Seattle, Kenneth S. McElvain, Menlo Park, Calif., and Kenneth R. McElvain, Houston, for a "timing-optimal placement, pin assignment, and routing for integrated circuits." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques for timing-optimal placement, pin assignment, and routing for integrated circuits are described herein. According to one embodiment, a list of paths providing implementation possibilities is constructed. A means is provided for removing paths from the list as well as a means for committing paths to the implementation if such paths are required for making the circuit implementation valid. Paths with worst case attributes are iteratively removed from the list until all paths in the list are committed to the implementation. Other methods and apparatuses are also described." The patent application was filed on April 30, 2009 (12/433,476). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,077&OS=8,136,077&RS=8,136,077 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Sony Assigned Patent ALEXANDRIA, Va., March 14 -- Sony, Tokyo, and Sony Electronics, Park Ridge, N.J., have been assigned a patent (8,136,051) developed by Steven Friedlander, San Diego, and Hyehoon Yi, Escondido, Calif., for a "method and apparatus for automatically updating a primary display area." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Receiving commands from a remote controller and automatically activating display areas for cursor navigation. Content display areas within a display frame respectively correspond to a variety of content items and include a primary display area wherein cursor navigation is activated and secondary display areas wherein cursor navigation is prevented. Remote controller navigational commands, for example, then allow cursor based navigation for the content item currently displayed in the primary display area. A content selection command such as a number key input of the remote controller allows immediate and automatic updating of the primary display area to include a desired content item that is associated to the command (e.g., the particular number)." The patent application was filed on March 13, 2009 (12/382,324). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,051&OS=8,136,051&RS=8,136,051 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Adobe Systems Assigned Patent ALEXANDRIA, Va., March 14 -- Adobe Systems, San Jose, Calif., has been assigned a patent (8,136,100) developed by Oliver Goldman, Redwood City, Calif., for a "software installation and icon management support." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods, systems, and apparatus, including medium-encoded computer program products, for software installation and icon management support. In one aspect, a method includes obtaining a cross-platform package of information stored in a platform independent format, the cross-platform package information including a cross-platform icon and one or more descriptors for the cross-platform icon; translating the cross-platform icon to a predefined icon format for a specific operating system (OS) on a computer; and providing the translated icon in the predefined icon format for display by the OS on the computer." The patent application was filed on July 5, 2007 (11/773,884). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,100&OS=8,136,100&RS=8,136,100 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Green Hills Software Assigned Patent ALEXANDRIA, Va., March 14 -- Green Hills Software, Santa Barbara, Calif., has been assigned a patent (8,136,096) developed by seven co-inventors for a "backward post-execution software debugger." The co-inventors are Michael Lindahl, Santa Barbara, Calif., Andre Yew, Santa Barbara, Calif., Mallory Morgan Green, II, Santa Barbara, Calif., Michael Johnson, Goleta, Calif., Allan Craig Franklin, Santa Barbara, Calif., Daniel O'Dowd, Santa Barbara, Calif., and Neil Puthuff, Ladera Ranch, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method finds an error in a computer program. A plurality of execution breakpoints are set in the computer program. A portion of the execution of the computer program is simulated as recorded in the trace data in the reverse order until one a plurality of conditions is met, wherein one of the plurality of conditions is an attempt to execute a machine instruction associated with one of the plurality of execution breakpoints." The patent application was filed on July 23, 2004 (10/897,749). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,096&OS=8,136,096&RS=8,136,096 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Hewlett-Packard Development Assigned Patent ALEXANDRIA, Va., March 14 -- Hewlett-Packard Development, Houston, has been assigned a patent (8,136,085) developed by Peter Skillman, San Carlos, Calif., Kevin Michael O'Shaughnessy, Galway, Ireland, and Sung-ho Park, Santa Clara, Calif., for a "system and method for implementing a shared platform or software resource for coupled computing devices." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A computing device includes a communication port, memory resources, and one or more processors. The one or more processors are configured to combine with the memory resources to operate one or more of the plurality of modules. The plurality of modules are operative in order to handle exchange of communications with a primary computer over the communication port. The one or more modules include a first module that is operative in a first communication mode in enabling exchange of communications with the primary computer over the communication port. The exchange of communications causes the primary computer to access and execute one or more autorun files from the computing device. The one or more modules may also include a second module that is operative in a second communication mode to be operative in enabling an alternative function to be performed with or for the primary computer over the communication port." The patent application was filed on May 14, 2008 (12/152,656). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,085&OS=8,136,085&RS=8,136,085 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Cadence Design Systems Assigned Patent for Method and System for Incorporation of Patterns and Design Rule Checking ALEXANDRIA, Va., March 14 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,136,056) developed by Louis K. Scheffer, Campbell, Calif., and David C. Noice, Palo Alto, Calif., for a "method and system for incorporation of patterns and design rule checking." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes "known good" patterns, which chip fabricators know from experience are successful, and "known bad" patterns, which chip fabricators know to be unsuccessful. The pattern library can be used to contain exceptions to specified design rules, or to replace the design rules completely. In some implementations, the pattern library contains statistical information that is used to contribute to an overall figure of merit for the design. In other implementations, a routing tool may generate a plurality of possible IC layouts, and select one IC layout based on information contained in the pattern library." The patent application was filed on May 19, 2006 (11/437,320). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,056&OS=8,136,056&RS=8,136,056 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Scintera Networks Assigned Patent ALEXANDRIA, Va., March 14 -- Scintera Networks, Sunnyvale, Calif., has been assigned a patent (8,136,081) developed by Arvind V. Keerthi, Bangalore, India, and Prashant Choudhary, Milpitas, Calif., for a "method and apparatus to optimize adaptive radio-frequency systems." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A performance optimizing circuit is provided for a signal processing system which is parameterized by a set of coefficients that vary the operational characteristics of the signal processing system. The performance optimizing circuit receives as input a reference signal and an output signal of the signal processing system. The performance optimizing circuit may include (a) a cost computation circuit that receives the reference signal and the output signal and provides as output a cost signal representing a cost function computed using a set of current values for the set of coefficients, the output signal and the reference signal; and (b) a cost optimizer circuit that, at each of a plurality of successive time intervals, evaluates one or more values of the cost signal in the cost computation circuit and provides to the signal processing system a new set of values for the set of coefficients. The cost optimizer circuit implements two or more of the random search, parabolic interpolation and hill climbing techniques." The patent application was filed on April 16, 2010 (12/762,098). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,081&OS=8,136,081&RS=8,136,081 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Xilinx Assigned Patent ALEXANDRIA, Va., March 14 -- Xilinx, San Jose, Calif., has been assigned a patent (8,136,075) developed by Satyaki Das, Palo Alto, Calif., and Christopher H. Kingsley, Longmont, Colo., for a "multilevel shared database for routing." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A multilevel shared database for routing for an integrated circuit is described. An aspect relates generally to a database comprising routing edges defined by tile templates. The routing edges are associated with a plurality of wire length segmentations. The tile templates are associated with tiles of an integrated circuit. The tiles are repeated circuit blocks forming an array. A portion of the tile templates are shared among a portion of the tiles such that the tile templates are less in number than the tiles. The tile templates are associated with pointers for pointing to wire templates." The patent application was filed on Nov. 7, 2008 (12/267,058). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,075&OS=8,136,075&RS=8,136,075 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Cadence Design Systems Assigned Patent ALEXANDRIA, Va., March 14 -- Cadence Design Systems, San Jose, Calif., has been assigned a patent (8,136,068) developed by four co-inventors for "methods, systems, and computer program products for implementing compact manufacturing models in electronic design automation." The co-inventors are Li J. Song, Fremont, Calif., Srini Doddi, Fremont, Calif., Emmanuel Drego, Los Gatos, Calif., and Nickhil Jakatdar, Los Altos, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodiments, the method or the system receives or identifies the physics based data for the corresponding manufacturing process by using the golden manufacturing process model. In some embodiments, the method or the system uses the physics based data to fine tune, modify, or adjust the golden manufacturing process model. In some embodiments, the method or the system invokes the just-right module. In some embodiments, the method or the system implements the compact manufacturing model and the correct-by-design module and provides guidelines for the various stages of the electronic circuit design." The patent application was filed on Sept. 30, 2008 (12/242,442). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,068&OS=8,136,068&RS=8,136,068 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Nuance Communications Assigned Patent ALEXANDRIA, Va., March 14 -- Nuance Communications, Burlington, Mass., has been assigned a patent (8,136,050) developed by Heiko K. Sacher, Menlo Park, Calif., Maria E. Romera, San Jose, Calif., and Jens Nagel, San Francisco, for an "electronic device and user interface and input method therefor." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A portable electronic device (100,400) and user interface (425) are operated using a method including initiating entry of a content string; determining the most probable completion alternative or a content prediction using a personalized and learning database (430); displaying the most probable completion alternative or next content prediction; determining whether a user has accepted the most probable completion alternative or next content prediction; and adding the most probable completion alternative or next content prediction to the content string upon user acceptance." The patent application was filed on Nov. 21, 2003 (10/719,576). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,050&OS=8,136,050&RS=8,136,050 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Google Assigned Patent for Direct, Gesture-based Actions from Device's Lock Screen ALEXANDRIA, Va., March 14 -- Google, Mountain View, Calif., has been assigned a patent (8,136,053) developed by James B. Miller, Sunnyvale, Calif., and Jean-Michel Trivi, Boulder Creek, Calif., for a "direct, gesture-based actions from device's lock screen." The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments enable a mobile device to execute an action analogous to a user-defined action in response to receipt of a gesture analogous to a user-defined gesture. In a first embodiment, a computer-implemented method executes an action on a mobile device. A lock screen view is displayed on the mobile device to prevent unauthorized and inadvertent access to the mobile device's data. While the mobile device is locked, a touch gesture having a pre-defined shape is detected on a touch screen of the mobile device independently of the initial position of the touch gesture on the touch screen. In response to detection of the touch gesture, a particular action is executed on the mobile device while the mobile device stays locked. The particular action determined according to the pre-defined shape. In this way, detection of the touch gesture causes the particular action to execute while keeping the mobile device locked." The patent application was filed on June 28, 2011 (13/170,798). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,053&OS=8,136,053&RS=8,136,053 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Xilinx Assigned Patent for Circuit Design Fitting ALEXANDRIA, Va., March 14 -- Xilinx, San Jose, Calif., has been assigned a patent (8,136,073) developed by Sankaranarayanan Srinivasan, San Jose, Calif., and Damon McCormick, San Jose, Calif., for a circuit design fitting. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Circuit design fitting for an integrated circuit is described. A mapped design for the circuit design is obtained. A first placement of the mapped design in association with an integrated circuit is performed. Circuit blocks are marked associated with the integrated circuit with control set identifiers. A circuit object is associated with a control set identifier. A site for placement of the first circuit object is located. The site is associated with a circuit resource block, which is associated with circuit resource blocks of the integrated circuit. Nearest neighbor circuit resource blocks with respect to the circuit resource block are acquired. The nearest neighbor circuit resource blocks of the circuit resource block are categorized in response to statuses. The circuit object is placed in a nearest neighbor of the nearest neighbor circuit resource blocks of the circuit resource block for a second placement." The patent application was filed on April 24, 2009 (12/429,842). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,073&OS=8,136,073&RS=8,136,073 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** INPA Systems Assigned Patent ALEXANDRIA, Va., March 14 -- INPA Systems, San Jose, Calif., has been assigned a patent (8,136,065) developed by Thomas B. Huang, San Jose, Calif., and Chioumin M. Chang, San Jose, Calif., for an "integrated prototyping system for validating an electronic system design." The abstract of the patent published by the U.S. Patent and Trademark Office states: "An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator." The patent application was filed on April 25, 2008 (12/110,233). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,136,065&OS=8,136,065&RS=8,136,065 Written by Satyaban Rath; edited by Hemanta Panigrahi. *** Apple Assigned Patent ALEXANDRIA, Va., March 14 -- Apple, Cupertino, Calif., has been assigned a patent (8,135,727) developed by nine co-inventors for "methods and systems for managing data." The co-inventors are Yan Arrouye, Mountain View, Calif., Dominic Giampaolo, Mountain View, Calif., Bas Ording, San Francisco, Gregory Christie, San Jose, Calif., Stephen Olivier Lemay, San Francisco, Marcel Van Os, San Francisco, Imran Chaudhri, San Francisco, Kevin Tiene, Cupertino, Calif., and Pavel Cisler, Los Gatos, Calif. The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and systems for processing data, including metadata and an index database. In one exemplary method, a first folder, representing a first search query, is stored, and a second folder, representing a second search query wherein the second folder has a predetermined hierarchical relationship to the first folder, is stored, and the search queries are used to search one or both of an index database and a metadata database. In the metadata database, the type of metadata for one file type differs from the type of metadata for another file type." The patent application was filed on Aug. 6, 2010 (12/852,441). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,135,727.PN.&OS=PN/8,135,727&RS=PN/8,135,727 Written by Shabnam Sheikh; edited by Jaya Anand. *** Yahoo! Assigned Patent ALEXANDRIA, Va., March 14 -- Yahoo!, Sunnyvale, Calif., has been assigned a patent (8,135,725) developed by Joshua Schachter, Mountain View, Calif., for a "system and method for providing tag-based relevance recommendations of bookmarks in a bookmark and tag database." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method comprises identifying a first user having stored in a database a set of first bookmarks associated with a topic of interest; determining a level of relatedness of a second user to the first user by comparing a first number of overlapping bookmarks that were stored in the database by the second user and that overlap the set of first bookmarks; determining a level of value of the second user to the first user by comparing a second number of related nonoverlapping bookmarks that were stored in the database by the second user, that relate to the topic of interest, and that do not overlap the set of first bookmarks; and presenting at least a portion of the related nonoverlapping bookmarks to the first user." The patent application was filed on Aug. 11, 2006 (11/503,051). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,135,725.PN.&OS=PN/8,135,725&RS=PN/8,135,725 Written by Shabnam Sheikh; edited by Jaya Anand. *** Tellabs San Jose Assigned Patent ALEXANDRIA, Va., March 14 -- Tellabs San Jose, Naperville, Ill., has been assigned a patent (8,135,878) developed by Naveen K. Jain, San Jose, Calif., for a "method and apparatus for improving throughput on a common bus." The abstract of the patent published by the U.S. Patent and Trademark Office states: "A bus scheduling device having a group of direct memory access ("DMA") engines, a group of target modules ("TM"), a read pending memory, and a bus arbiter is disclosed. A common bus, which is coupled with the DMA engines, TMs, and the read pending memory, is employed in the device for data transmission. DMA engines are capable of transmitting and receiving data to and from TMs via the common bus. The read pending memory is capable of storing information indicating the read status of the DMA engines. The arbiter or bus arbiter arbitrates For more information about Targeted News Service products and services, please contact: Myron Struck, editor, Targeted News Service LLC, Springfield, Va., 703/304-1897; [email protected]; http://targetednews.com. -1078914 (c) 2012 Targeted News Service |