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Use auto-zero comparator techniques to improve PWM performance(Electronic Engineering Times Via Acquire Media NewsEdge) Comparators are subject to input offset errors that can be either systematic or layout-related. Two applications of comparators in a PWM controller are detecting when there is no current in the inductor and detecting when there is no current in the main control-loop comparator. During the discontinuous conduction mode of the converter, the comparator must detect when the inductor current reverses through the lower-power MOSFET. This is done by comparing the drain voltage of the MOSFET during its on time to the ground reference. The use of an auto-zeroing comparator will eliminate the offset variation and, therefore, improve the accuracy of the zero-current detection. For the main PWM comparator, the use of an auto-zeroing comparator eliminates the control-loop offset between the error amplifier and the ramp-crossing level, thereby improving the overall system performance, especially at duty cycles that are less than 5 percent. Lower power and high efficiency are the key priorities in power management today. Portable electronics need to conserve battery power and operate over a wide range of input voltages. For PWM voltage regulators designed into portable systems, those requirements present design challenges as well as opportunities. Two such opportunities exist for the use of auto-zeroing comparators in the design of power management systems. Using conventional CMOS comparators, such as the one shown in Figure 1, leads to complications in the design as well as the layout, in order to keep offsets to a minimum. Auto-zeroing comparators can be used to minimize system offsets and improve the performance of the regulator system. Sensing comparator An important function of a voltage-regulator system is the ability to maximize power efficiency at various levels of load currents. One way of achieving this is for the regulator to know when it is running in the low-power, variable-frequency pulse mode during discontinuous conduction operation (inductor current goes to zero) and when to change into the fixed-frequency PWM mode for operation in the continuous conduction region (inductor current is always greater than zero). During the variable-frequency operation mode, the regulator will output pulses in response to the ripple current through the inductor. This mode of operation is used during low-current loading because the low-side FET can be turned off when the reverse current through the inductor is allowed to go to zero. At low current levels, this mode of operation is more efficient than the PWM mode. A hysteretic comparator is used to compare the output voltage to a reference plus some degree of hysteresis. As the current load increases, the frequency of the control pulses increases as the output crosses the hysteresis threshold more frequently. One of the problems with this architecture is that the system must be able to determine when the inductor current enters into the discontinuous conduction mode of operation. This can be accomplished by placing a comparator that looks across the switch node, SW, and compares the voltage across the drain-source node of the low-side FET with ground. Figure 2 shows a block diagram of a typical application for a switch node RDSON sensing comparator. In the figure, Transistor M1 is the high-side MOSFET, and transistor M2 is the low-side MOSFET. As the inductor current passes through zero and becomes negative during the time that the low-side FET M2 is turned on, the voltage on the drain of the FET becomes positive. The comparator senses this change and reports back to the system that a discontinuous event has occurred. Most systems will count the number of times that the comparator reports this condition, and after perhaps eight counts, the system will change modes. However, this type of a comparison for a conventional CMOS comparator (Figure 1) is a difficult challenge. The comparator must be able to respond to a few millivolts of input signal from the drain of the low-side FET in the presence of large amounts of ground noise. If we take the example of a PWM regulator with a nominal output current of 5 A, we would like to set the discontinuous mode transition to begin at 0.1 x IOUT, or 0.5 A. If we choose a low-side power MOSFET with an RDSON of 40 milliohms, then the comparator will be looking at a signal of 0.5 A/2 x 0.04 = 10 mV. For CMOS IC comparators, offsets can easily be in the 8- to 12-mV range or higher, depending on the layout. This variation will cause a wide distribution regarding where the controller senses the crossover point between continuous conduction and discontinuous conduction regions of operation, thus leading to possible yield loss. Designing a conventional CMOS comparator to handle this job requires offset trimming and very careful layout. This type of comparator application is well-suited to an auto-zeroing comparator. Figure 3 shows a simplified schematic of an auto-zeroing comparator. The auto-zero comparator circuit is controlled by the DRIVE signal. During the auto-zeroing phase of operation, DRIVE is high, and MN1 is connected across C1 by closing switch S1 and connecting switch S2 to ground. During this time, the voltage of MN1 is stored across the storage capacitor C1. During the sampling phase of operation, the DRIVE signal is low, and switch S1 is open. Switch S2 now becomes connected to the input node, SW. When SW is below 0 V, MN1 is pinched off by the voltage on C1, allowing I1 to pull up on the drain of MN1. Once SW crosses 0 V, MN1 turns on and begins to pull down the gate of MN2, thus causing the COMPOUT node to change state. The obvious advantage of this circuit is to null the part-to-part variations in the offset of transistor MN1. The input to the comparator is connected to ground during the noisy transition between the high-side power FET's turning off and the low-side power FET's turning on. The DRIVE signal is only changed to the sample mode when the low-side FET is in the full-on condition. A further advantage of this architecture is that the comparator input is disconnected from the SW node during the time that the high-side FET is on. In a portable computer application, the SW node voltage could go as high as the charger output voltage, of around 20 V. Using a conventional comparator, you would need to place an additional high-voltage switch in series with the comparator input in order to protect it. PWM comparator Another application of auto-zeroing comparators is in the main control loop of a PWM system. The comparator in this application looks at the difference between a reference level and the output of the loop error amplifier. Figure 4 shows a simplified schematic of a PWM control loop. Most comparators will have a systematic offset that can be minimized by keeping the comparator gain high; however, offsets can be introduced during the layout phase of the comparator design. While these offsets are canceled out for the most part in the closed-loop system, comparator offsets can become important when the duty cycle of the system becomes very small. Portable electronic systems, such as laptop computers, increasingly fall into this category of PWM systems because the battery-charger output voltage is typically around 20 V, while the regulated supply voltages on the memory chips and processors needs to be around 1 V. This set of voltages will create a duty cycle of VOUT/VIN equal to 5 percent. Under this condition, the comparator will be working at the bottom of the PWM ramp, where the slope of the ramp is smallest and the pulse width to be processed out of the comparator will be very narrow. If the system clock is running at 600 kHz, the comparator must be able to support a pulse width of 1.67 ms/20, or about 83 ns. This situation is depicted in Figure 5. Any offset in the comparator that causes that number to become smaller can create instability in the control loop and force the system to compensate by alternating wide pulses and narrow pulses in order to maintain the duty cycle. This shows up as pulse jitter and will cause a larger ripple voltage at the output of the converter. In its most severe case, the comparator might miss a pulse cycle altogether, causing a subharmonic condition. With the auto-zeroing comparator, the system can be in the offset-sampling mode during the time that the PWM ramp is at the bottom of the ramp, and then switched to the input-sampling mode at the start of the ramp. The auto-zeroing comparator system can detect millivolt differences and thus be able to maintain very small pulse widths in very low-duty-cycle PWM systems. Figure 6 shows a simulation of a PWM system using a conventional CMOS-comparator design. The simulation shows the difference between the crossing levels of the ramp at the input to the PWM comparator and the actual error voltage at the input to the comparator. The difference between the two is the comparator offset. In the case of Figure 6, the offset is around 25 mV. This offset will limit the range of usable ramp for a stable system at very low duty cycles. Variations in the slope of the ramp will also contribute to the loop offset. In systems designed to operate from a battery, most PWM controllers will include a "feed forward" path from the battery that will sense the battery voltage and adjust the slope of the ramp compensation in order to keep the system stable. If the PWM comparator has additional offsets, then as the battery voltage changes, the system can experience regions of instability, which show up as jitter or alternating wide and narrow PWM pulses. In Figure 7, the auto-zeroing comparator has significantly less systematic offset and therefore allows the system to behave with better stability throughout the range of duty cycles. With the emphasis on highly efficient portable electronics with longer battery life, system designers must be aware of all the techniques that can be used to improve both the efficiency and accuracy of the system voltages that supply the circuits in those systems. The use of the auto-zeroing comparator to extend the operating range of PWM control systems is one more tool in the designer's kit of techniques to improve the accuracy and performance of PWM systems. Stephen W. Bryson is a principal design engineer at Fairchild Semiconductor Corp. (San Jose, Calif.). He has published several papers and has patents in the area of power management and drivers. He holds a BSEE from Oregon State University and MSEE from Santa Clara University. http://www.eet.com Copyright 2008 United Business Media LLC. All rights reserved. Copyright ? 2008 CMP Media LLC |