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March 25, 2011

Xelerated Adds HX336 Wirespeed Single-Chip NPU to HX Network Processor Family

By Nathesh, TMCnet Contributor


Xelerated, provider of network processing and programmable Ethernet switching solutions, added HX336, a wirespeed single-chip NPU with advanced traffic management and deep packet buffering for 100GbE/OTU4 systems to its HX family of network processors (NPUs).

Based on Xelerated’s (News - Alert) Dataflow Architecture, the HX family of NPUs are claimed to have the ability to raise the industry bar for performance and level of integration, empowering a new wave of high service density to Metro Ethernet systems. It provides 50 or 100 Gbps at wirespeed performance with a guaranteed number of operations and classification resources per packet, regardless of packet size and type.

The HX336 integrates packet processing, switching and traffic management for a single port of 100 Gbps. Like the other members of the HX family NPUs, HX336 also integrates Ethernet MACs, programmable switching and advanced traffic management for the delivery of fine-granular Quality of Service (QoS). The result is a single-chip solution with extraordinary service density, enabling system vendors to design products for more advanced Ethernet and IP services. The presence of 448 highly optimized Packet Instruction Set Computer processor cores where both packet data and instructions are locally available can remove expensive load/store operations.

Bob Wheeler, senior analyst at The Linley Group asserted that system vendors are facing significant power budget restrictions when moving from 10GbE to 40GbE and 100GbE solutions. Continued innovation in optics, packet processing and buffering will be required to make 100GbE commercially successful. Xelerated’s unique design is an example of an NPU, which is addressing the very root of the problem.

All Xelerated solutions are based on the same pipelined, programmable Dataflow Architecture, an architecture that is Wirespeed by design, cutting out time-consuming performance optimization commonly required in development of carrier-grade data planes. And the HX NPUs are allegedly designed from the ground up to simplify development of Carrier Ethernet platforms, ranging from full-fledged edge routers to packet-optical transport equipment and uplink cards in fiber access systems.


Nathesh is a contributing editor for TMCnet. To read more of Nathesh's articles, please visit his columnist page.

Edited by Jaclyn Allard




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