IBM Uses Water-Cooling to Design "Green" Data Centers

IBM (News - Alert) announced today that its labs have significantly reduced the power consumed by data centers by stacking circuits and components one above another and using tiny streams of water to cool those computer chips.

 

IBM officials say they’ve worked with the Fraunhofer Institute in Berlin to design a trial product that combines the cooling system into the 3-D chips by piping water directly between each layer in the stack.

 

3-D chip stacks are the ones that have silicon wafers piled on top of each other, rather than the traditional side-by-side placement. They’ve proved to be one of the most promising approaches to enhancing chip performance beyond its predicted limits, company officials say.

 

“As we package chips on top of each other to significantly speed a processor’s capability to process data, we have found that conventional coolers attached to the back of a chip don’t scale. In order to exploit the potential of high-performance 3-D chip stacking, we need interlayer cooling,” said Thomas Brunschwiler, project leader at IBM’s Zurich Research Laboratory. “Until now, nobody has demonstrated viable solutions to this problem.”

 

The 3-D chip stacks follow IBM’s advanced chip-stacking technology in a manufacturing environment modeled one year ago – a technology that shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, than 2-D chips, company officials say.

 

3-D chip stacks would have a collective heat dissipation of close to 1 kilowatt – that’s 10 times greater than the heat generated by a hotplate with an area of 4 square centimeters and a thickness of about 1 millimeter, company officials say.

 

The water streams that are used for cooling are as thin as a human hair, and they run between the individual chip layers, allowing them to discard heat at the source itself, company officials say. Scientists say they’ve used the superior thermo-physical qualities of water to show a cooling performance of up to 180 W/cm2 per layer for a stack with a typical footprint of 4 cm2.

 

“This truly constitutes a breakthrough. With classic backside cooling, the stacking of two or more high-power density logic layers would be impossible,” said Bruno Michel, manager of the chip cooling research efforts at the IBM Zurich Lab.

 

The assembling of individual layers was done by thin-film soldering technique, according to the company. This technique is apt for getting good thermal contacts and electrical contacts without any shorts. The assembled stack is placed in a silicon cooling container similar to a miniature basin. The water is pumped into the container from one side and flows between the individual chip layers before exiting at the other side.