A recent white paper titled "Design Space Exploration of Network Processor (News - Alert) Architectures," written by Lothar Thiele, Samarjit Chakraborty, Matthias Gries and Simon Kunzli of the Computer Engineering and Networks Laboratory of the Swiss Federal Institute of Technology in Zurich, Switzerland, discusses "an approach to explore the design space for architectures of packet processing devices on the system level."

(Whew, there goes the ol' word count.)

Network processors usually consist of multiple processing units such as CPU cores, micro-engines, and dedicated hardware for compute-intensive tasks such as header parsing, table look-up and encryption/decryption, the authors note, adding that together with these, "there are also memory units, caches, interconnections, and I/O interfaces."

There are several characteristics which are specific to the packet processing domain, the authors say, adding that "these do not arise in other application areas such as classical digital signal processing -- although both domains involve the processing of event streams."

No, the packet processing case "is concerned with the processing of interleaved streams of data packets, where for each packet stream a certain sequence of tasks must be executed, so there are usually no recurrent or iterative computations, the tasks are of high granularity, and they are often scheduled dynamically at run-time."

Due to "this difference with other known target domains for system-level design space exploration," the authors say, "several new questions arise: How should packet streams, task structures and hardware and software resources appropriately be modeled? How can the performance of a network processor architecture be determined in the case of several (possibly conflicting) usage scenarios?"

Since, as they say, the design space can be very large, "what kind of strategy should be used to efficiently explore all options and to obtain a reasonable compromise between various conflicting criteria?"