A single-chip control/data-plane network processor combines control-plane and data-plane processing on a single chip.

In networking or communications equipment, the data plane processes each packet as it passes through the system. Data-plane errands may consist of converting packets from one protocol to another, encrypting or decrypting data, filtering unwanted packets, prioritizing packets, and routing them to their next destination.

A relatively simple processor with a small amount of software, therefore, can perform these tasks, but they must be done quickly. Packets must be processed at least at wire speed, that is, the speed of the incoming network connection. For example -- 1Gbps for a Gigabit Ethernet connection.

Because of the varying characteristics of control-plane and data-plane processing, these two tasks have typically been performed on separate chips. The control plane typically uses a general-purpose processor, which is simple to program and can conduct large amounts of code.

So to attain wirespeeds of 1Gbps or more, the data plane may use a device such as an ASIC, an FPGA, or a specialized network processor. The latter are specialized devices that increase throughput and reduce power dissipation compared with a general-purpose processor.

Of course today IC process technology is reaching 65nm, 45nm, and below -- which means the transistor budgets for leading-edge devices are rising rapidly. These budgets can easily accommodate numerous processors on a lone chip, along with all of the similar coprocessors and system interfaces.

Here’s where Moore’s Law is driving the integration of the control plane and data plane into a single device: the SCDP. This integration will occur first at the low end, where the processors require less die area and can simply be combined and move towards the high end as transistor budgets increase.