In a world of smart devices and connected everything, the expectation for our technology form factors is that everything will become smaller and more powerful over time, not to mention cheaper. But, with the 50th anniversary of Moore’s Law fast approaching, there’s some question about the sustainability of that trend as silicon enters the microscopic realm. But Intel (News - Alert) may have a solution.
Moore’s Law says that transistor density—that is, the number of transistors per square inch on integrated circuits--will double approximately every two years, allowing the chips that power our gear to get progressively faster and cheaper. The prediction was made in 1965 by Gordon Moore, co-founder of Intel. And now it’s Intel again, with new transistors and silicon innovation, which is looking to save Moore’s Law from turning back on itself.
The problem is that there’s only so small that you can go before electricity leakage and power management become issues, affecting both performance and cost, and throwing Moore’s Law out of whack.
“Scaling to future process technologies is increasingly challenging; Intel ran into yield problems at 14 nanometers, and many other companies are grumbling about the increase in wafer costs,” said David Kanter, an analyst at Linley Group, in an article. “At the same time, the performance and power benefits from shrinking to a new process have changed.”
As in, they’re beginning to disappear.
Kantar noted that historically, as power consumption of a transistor scaled down quadratically, overall power density stayed constant – even as the transistor density exploded. This phenomenon is known as Dennard scaling, after its discoverer. But sometime in the early 2000s, Dennard scaling broke down.
“Performance could no longer be increased through geometry alone, and power became a tremendous problem,” Kantar said.
Despite the power issue, scaling down physically is certainly happening. Right now, Intel makes chips using a 14-nanometer process, and is preparing its move to 10-nanometer later this year or early next. A 7-nanometer process is also in the pipeline, which is estimated to come into production in 2017 or 2018.
Intel, however, may have a plan. Power consumption comes in two varieties – static power, due to leakage from the current flowing through the transistors, and dynamic power, due to the switching activity that takes place in transistors. Kantar predicts that to solve the problem, Intel will move to something experimental that it’s been working on for a decade: Quantum (News - Alert) Well FET transistors, which partition the electrons that carry the current, in order to gain efficiencies in both arenas.
“Essentially, the FinFET geometry confines the electrons from three sides, with the bottom barrier handling the fourth side – creating a quantum well,” Kantar explained.
He believes this technology was headed out of research, into development, and ultimately into processors that would be on the market—thus preserving Moore’s Law.
“I believe that 10-nanometer is the most likely intercept point (it’s possible, but less likely, Intel will wait until 7nm), given the timing of the research and Intel’s historical cadence of new manufacturing technologies,” he said.
Edited by Rory J. Thompson