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Cadence Tapes Out 16G UCIe Advanced Package IP on TSMC's N3E Process TechnologyCadence Design Systems, Inc. (Nasdaq: CDNS) today announced the tapeout of Cadence® 16G UCIe™ 2.5D advanced package IP on TSMC's 3nm (N3E) process technology. Implemented on TSMC's 3DFabric™ CoWoS-S silicon interposer technology, the IP offers ultra-high bandwidth density, efficient low-power performance and superior low latency, making it ideal for applications requiring extreme compute power. Cadence UCIe IP provides an open standard for chiplet die-to-die communication, which is becoming more critical as artificial intelligence/machine learning (AI/ML), mobile, automotive, storage and networking applications are driving the need to move from monolithic integration to system-in-package (SiP) chiplets. Cadence is currently engaged with a pipeline of Tier 1 customers, and UCIe advanced package IP collateral from the N3E test chip tapeout is shipping and available. The pre-verified solution can save customers time and effort through rapid integration. The heterogeneous integration of Cadence's UCIe PHY and controller eases chiplet solutions with die reusability. The complete solution includes the following, which can be delivered with a complement of Cadence Verification IP (VIP) and TLM models:
"Cadence has been an industry pioneer in chiplet system solution offerings and continues to push the envelope of performance and power efficiency for a wide range of multi-chiplet applications in advanced nodes and packaging architectures," said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. "We see great value in aligning interconnect standards across the industry, and UCIe IP serves as a bridge, enabling open chiplet solutions for large SoCs reaching or exceeding the maximum reticle limit for manufacturing. The recent UCIe advanced package tapeout on the TSMC N3E process is a key milestone and commitment toward enabling customers with an open chiplet connectivity standard." The Cadence 16G UCIe™ 2.5D advanced package IP supports Cadence's Intelligent System Design™ strategy, which enables SoC design excellence. For more information, please visit: www.cadence.com/go/ucie16g. About Cadence Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For nine years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at www.cadence.com. © 2023 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. UCIe Consortium, Universal Chiplet Interconnect Express, and UCIe are trademarks of the UCIe Consortium. PCI Express and PCIe are registered trademarks or trademarks of PCI-SIG. SystemC is a trademark of Accellera Systems Initiative Inc. All other trademarks are the property of their respective owners. Category: Featured
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