DVCon U.S. 2023 Announces Stuart Sutherland Best Paper & Best Poster Winners

GAINESVILLE, Fla., March 08, 2023 (GLOBE NEWSWIRE) -- The 2023 Design and Verification Conference and Exhibition U.S. (DVCon U.S.), sponsored by Accellera Systems Initiative (Accellera), concluded its 35th annual event in San Jose, CA last week. The 2023 Best Paper and Poster winners, as voted on by attendees, were announced during a reception in the exhibit hall on March 1.

Participants came from 35 countries and represented approximately 275 companies, with 323 attending the conference and exhibition for the first time. Overall attendance for DVCon U.S. 2023 was approximately 850.

“We were thrilled to be back in person this year,” stated Vanessa Cooper, DVCon U.S. 2023 General Chair. "The energy and excitement from attendees was evident throughout the conference, especially during the new Poster Ninja Warrior Session. We had the top four poster presenters competing in front of a standing room only crowd with lively audience participation, creating an exciting and fun atmosphere for attendees. The exhibit hall was also bustling during receptions with many colleagues connecting face-to-face for the first time since 2020. Our technical sessions were also very well-attended with many topics to choose from for attendees. We are very proud that DVCon continues to be an important resource for the practicing design and verification engineer and that what they learn will help them be successful in their current and future projects.”

The award for the Stuart Sutherland Best Paper Presentation, as voted by conference attendees, went to Chuck McClish, Microchip Technology Inc. for “Take AIM! Introducing the Analog Information Model.” Second place winners Jun Yan and Josh Baylor, Renesas Electronics, presented “Automated Modeling Testbench Methodology Tested with four Types of PLL Models.” Rob Donnelly and Josh Geden, NASA Jet Propulsion Laboratory took third place for their paper, “Regvue: Modern Register Documentation.”

Top honors for best poster went to Robert Martin, Alan Curtis and Qingwei Zhou, Intel and Gopinath Narasimhan, Synopsys for “Improvement of UVM Scenario Generation, Control and Reproducibility using Portable Stimulus for IP Validation.” Eldhose PM, Suraj Shetty, Sagar Jayakrishnan, Kuntal Pandya, and Parag S. Lonkar, Samsung were awarded second place for, “An Enhanced DV Approach for Effectively Verifying High Speed, Low Power MIPI-MPHY5.0 Designs.” Woojoo Ki, Kunhyuk Kang and Seonil Brian Choi, Samsung took third place for, “A Study on Virtual Prototyping based Design Verification Methodology.”

Highlights of the Week: 

• The conference kicked off on Monday with Accellera Day featuring a morning tutorial on user experiences with the Portable Test and Stimulus Standard (PSS), as well as nine workshops throughout the day.
   
• Bob Smith, Director of SEMI/ESD Alliance presented, “The CHIPs Act and its Impact on the Design and Verification Industry,” during Monday’s luncheon.
   
• More than 200 attended the keynote on Tuesday, “What do farming, steel and space have in common?” presented by Dirk Didascalou, CTO Siemens Digital Industries. Dirk focused on the digital transformation taking place in the electronics industry and the need for companies to move away from an “ego” system and work together toward an ecosystem.
   
• There were two panels on Wednesday: “Systems are Evolving. Is Verification Keeping Up?” moderated by Bernard Murphy, SemiWiki. and “AI-ML Algorithms are Transforming Verification: Separating Hype from Reality,” moderated by Shankar Hemmady, CEO, Blue Horizons. Both sessions were well-attended and gave the audience an opportunity to ask questions of the panelists.
   
• The Accellera-sponsored luncheon on Wednesday had the presentation of the Accellera 2023 Technical Excellence Award posthumously awarded to Phil Moorby, the inventor of Verilog HDL. Some of his close colleagues shared stories and photos of their time with Phil, giving attendees a glimpse into the significant impact he made on the industry. The lunch concluded with Mark Himelstein, CTO of RISC-V International, giving a talk focused on “RISC-V Everywhere.”
   
• New to the program this year was the Poster Ninja Warrior Session to determine the Stuart Sutherland Best Poster Award winners. The top four posters went to battle in front of a standing room only crowd to see who would take top honors. Audience participation helped to decide the winners.

The DVCon Steering Committee values all feedback regarding the conference. DVCon U.S. attendees have been given a survey and are asked to provide input and feedback on how we can improve and continue to make DVCon the industry’s must-attend conference for design and verification engineers.

Save the date:  DVCon U.S. 2024 will be held March 4-7 at the DoubleTree Hotel in San Jose, California. Tom Fitzpatrick is appointed General Chair for DVCon U.S. 2024.

About DVCon
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit here. Follow DVCon on Facebook, LinkedIn or @dvcon_us on Twitter or to comment, please use #dvcon_us.

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